A Simple AXI4-Lite Slave

module axil_slave #(
  parameter int ADDR_W = 8,    // byte address width into this slave
  parameter int DATA_W = 32    // 32 or 64 for AXI4-Lite
) (
  input  logic                  aclk,
  input  logic                  aresetn,   // active-low
 
  // Write address channel
  input  logic [ADDR_W-1:0]     s_awaddr,
  input  logic                  s_awvalid,
  output logic                  s_awready,
  // Write data channel
  input  logic [DATA_W-1:0]     s_wdata,
  input  logic [DATA_W/8-1:0]   s_wstrb,
  input  logic                  s_wvalid,
  output logic                  s_wready,
  // Write response channel
  output logic [1:0]            s_bresp,
  output logic                  s_bvalid,
  input  logic                  s_bready,
 
  // Read address channel
  input  logic [ADDR_W-1:0]     s_araddr,
  input  logic                  s_arvalid,
  output logic                  s_arready,
  // Read data channel
  output logic [DATA_W-1:0]     s_rdata,
  output logic [1:0]            s_rresp,
  output logic                  s_rvalid,
  input  logic                  s_rready
);

typedef enum logic [1:0] { W_IDLE, W_WRITE, W_RESP } wstate_e;
wstate_e wstate;
 
logic [ADDR_W-1:0] awaddr_q;
logic              aw_done, w_done;
logic [DATA_W-1:0] wdata_q;
logic [DATA_W/8-1:0] wstrb_q;
 
// Accept AW and W independently while in IDLE
assign s_awready = (wstate == W_IDLE) && !aw_done;
assign s_wready  = (wstate == W_IDLE) && !w_done;
 
always_ff @(posedge aclk) begin
  if (!aresetn) begin
    wstate <= W_IDLE; aw_done <= 1'b0; w_done <= 1'b0;
    s_bvalid <= 1'b0; s_bresp <= 2'b00;
  end else begin
    // Latch address/data as each handshake completes
    if (s_awvalid && s_awready) begin awaddr_q <= s_awaddr; aw_done <= 1'b1; end
    if (s_wvalid  && s_wready ) begin wdata_q <= s_wdata; wstrb_q <= s_wstrb; w_done <= 1'b1; end
 
    case (wstate)
      W_IDLE: if ((aw_done || (s_awvalid && s_awready)) &&
                  (w_done  || (s_wvalid  && s_wready ))) wstate <= W_WRITE;
      W_WRITE: begin
        // Address decode + WSTRB-masked write happen here (see §4)
        s_bresp  <= decode_err ? 2'b11 /*DECERR*/ : 2'b00 /*OKAY*/;
        s_bvalid <= 1'b1;
        wstate   <= W_RESP;
      end
      W_RESP: if (s_bvalid && s_bready) begin
        s_bvalid <= 1'b0; aw_done <= 1'b0; w_done <= 1'b0;
        wstate <= W_IDLE;
      end
    endcase
  end
end

typedef enum logic { R_IDLE, R_RESP } rstate_e;
rstate_e rstate;
 
assign s_arready = (rstate == R_IDLE);
 
always_ff @(posedge aclk) begin
  if (!aresetn) begin
    rstate <= R_IDLE; s_rvalid <= 1'b0; s_rresp <= 2'b00;
  end else begin
    case (rstate)
      R_IDLE: if (s_arvalid && s_arready) begin
        // Decode s_araddr, read register into s_rdata (see §4)
        s_rresp  <= rdecode_err ? 2'b11 : 2'b00;
        s_rvalid <= 1'b1;
        rstate   <= R_RESP;
      end
      R_RESP: if (s_rvalid && s_rready) begin
        s_rvalid <= 1'b0;
        rstate   <= R_IDLE;
      end
    endcase
  end
end

logic [DATA_W-1:0] reg_ctrl;       // RW
logic [DATA_W-1:0] reg_status;     // RO (driven by hardware)
logic decode_err, rdecode_err;
 
// --- Write commit (inside W_WRITE), word offset = awaddr_q[ADDR_W-1:2] ---
always_comb decode_err = 1'b0;
always_ff @(posedge aclk) begin
  if (aresetn && wstate == W_WRITE) begin
    case (awaddr_q[ADDR_W-1:2])
      'h0: for (int b = 0; b < DATA_W/8; b++)
             if (wstrb_q[b]) reg_ctrl[b*8 +: 8] <= wdata_q[b*8 +: 8];
      'h1: ; // STATUS is read-only: ignore the write data, respond per policy
      default: decode_err <= 1'b1;   // unmapped → DECERR
    endcase
  end
end
 
// --- Read mux (registered into s_rdata at AR handshake) ---
always_ff @(posedge aclk) begin
  if (aresetn && rstate == R_IDLE && s_arvalid && s_arready) begin
    rdecode_err <= 1'b0;
    case (s_araddr[ADDR_W-1:2])
      'h0: s_rdata <= reg_ctrl;
      'h1: s_rdata <= reg_status;
      default: begin s_rdata <= '0; rdecode_err <= 1'b1; end  // DECERR
    endcase
  end
end