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VHDL Labs
Lab 12of 30
Combinational RTL Design6
Sequential Logic6
FSM & Control Design6
Datapath & Memory6
Advanced RTL & Verification6
Sequential LogicPublished
Universal Shift Register
Hold, shift left, shift right or parallel-load under a mode select, and verify every mode against a software model.
Intermediate~45 minSelf-checking testbench
Concepts covered
- Mode select
- Serial inputs
- Parallel load
- Randomised stimulus
This lab is part of VHDL Labs
Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.
- Problem statement & specification
- Complete VHDL-2008 RTL
- Self-checking testbench
- Simulation transcript & waveform
- Measured design mistakes
- Verification checklist