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Lab 2of 30
Combinational RTL Design6
Sequential Logic6
FSM & Control Design6
Datapath & Memory6
Advanced RTL & Verification6
Combinational RTL DesignPublished
2:1 and 4:1 Multiplexer
Build a 2:1 and a 4:1 multiplexer with selected and conditional assignments, and see why a complete choice list matters.
Beginner~35 minSelf-checking testbench
Concepts covered
- with/select
- when/else
- Complete choices
- Generic width
This lab is part of VHDL Labs
Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.
- Problem statement & specification
- Complete VHDL-2008 RTL
- Self-checking testbench
- Simulation transcript & waveform
- Measured design mistakes
- Verification checklist