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Lab 11of 30

  1. Combinational RTL Design6

  2. Sequential Logic6

  3. FSM & Control Design6

  4. Datapath & Memory6

  5. Advanced RTL & Verification6

Sequential LogicPublished

Mod-10 Counter

Count 0 to 9 with a terminal-count output, recover from illegal values, and cascade two counters into a decade pair.

Intermediate~40 minSelf-checking testbench
Concepts covered
  • Terminal count
  • Modulo wrap
  • Illegal-state recovery
  • Cascading
This lab is part of VHDL Labs

Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.

  • Problem statement & specification
  • Complete VHDL-2008 RTL
  • Self-checking testbench
  • Simulation transcript & waveform
  • Measured design mistakes
  • Verification checklist
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