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Combinational RTL Design6
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Combinational RTL DesignPublished
Basic Logic Gates
Describe AND, OR, NOT, NAND, NOR, XOR and XNOR as concurrent signal assignments and prove all seven against an exhaustive truth table.
Beginner~30 minSelf-checking testbench
Concepts covered
- entity/architecture
- Concurrent assignment
- std_logic
- Exhaustive testing
This lab is part of VHDL Labs
Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.
- Problem statement & specification
- Complete VHDL-2008 RTL
- Self-checking testbench
- Simulation transcript & waveform
- Measured design mistakes
- Verification checklist