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Combinational RTL Design6
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Combinational RTL DesignPublished
2-to-4 Decoder with Enable
Decode two address bits into one-hot outputs gated by an enable, and verify the outputs are all-zero whenever the enable is low.
Beginner~30 minSelf-checking testbench
Concepts covered
- One-hot outputs
- Enable gating
- case statement
- Process sensitivity
This lab is part of VHDL Labs
Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.
- Problem statement & specification
- Complete VHDL-2008 RTL
- Self-checking testbench
- Simulation transcript & waveform
- Measured design mistakes
- Verification checklist