Register File with Two Read Ports

Build a register file with one synchronous write and two asynchronous reads, and define what a same-cycle read returns.

Intermediate~50 minSelf-checking testbench

Concepts covered

Array types
Read-during-write
Hardwired zero register
Port independence

This lab is part of VHDL Labs

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Problem statement & specification
Complete VHDL-2008 RTL
Self-checking testbench
Simulation transcript & waveform
Measured design mistakes
Verification checklist

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Combinational RTL Design6

Sequential Logic6

FSM & Control Design6

Datapath & Memory6

Advanced RTL & Verification6

Register File with Two Read Ports