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Lab 27of 30
Combinational RTL Design6
Sequential Logic6
FSM & Control Design6
Datapath & Memory6
Advanced RTL & Verification6
Advanced RTL & VerificationPublished
SPI Master Controller
Drive a mode-0 SPI transfer with chip select, clock and MOSI, capture MISO, and verify both directions with a slave model.
Advanced~60 minSelf-checking testbench
Concepts covered
- SPI mode 0
- Clock divider
- Full-duplex shift
- Slave model
This lab is part of VHDL Labs
Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.
- Problem statement & specification
- Complete VHDL-2008 RTL
- Self-checking testbench
- Simulation transcript & waveform
- Measured design mistakes
- Verification checklist