All VHDL labs
VHDL Labs
Lab 28of 30
Combinational RTL Design6
Sequential Logic6
FSM & Control Design6
Datapath & Memory6
Advanced RTL & Verification6
Advanced RTL & VerificationPublished
Clock-Domain Crossing Pulse Synchronizer
Move a single-cycle pulse between unrelated clocks with a toggle synchroniser, and state precisely what simulation cannot prove.
Advanced~55 minSelf-checking testbench
Concepts covered
- Toggle synchroniser
- Two-flop synchroniser
- Pulse spacing
- Limits of simulation
This lab is part of VHDL Labs
Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.
- Problem statement & specification
- Complete VHDL-2008 RTL
- Self-checking testbench
- Simulation transcript & waveform
- Measured design mistakes
- Verification checklist