All VHDL labs
VHDL Labs
Lab 5of 30
Combinational RTL Design6
Sequential Logic6
FSM & Control Design6
Datapath & Memory6
Advanced RTL & Verification6
Combinational RTL DesignPublished
Half Adder and Full Adder
Derive sum and carry from first principles, compose a full adder from two half adders, and check against integer arithmetic.
Beginner~35 minSelf-checking testbench
Concepts covered
- Structural instantiation
- Component reuse
- Port maps
- Arithmetic oracle
This lab is part of VHDL Labs
Unlock the complete lab — specification, engineering explanation, VHDL-2008 RTL, a self-checking testbench, the simulation transcript and waveform, measured design mistakes and a verification checklist — with the VHDL Labs package.
- Problem statement & specification
- Complete VHDL-2008 RTL
- Self-checking testbench
- Simulation transcript & waveform
- Measured design mistakes
- Verification checklist