VHDL Design & Simulation Labs.
Design, simulate, verify and debug practical digital circuits in VHDL-2008 — from gates and flip-flops through state machines, memories and serial interfaces to clock-domain crossing and automated regression. Every lab states the hardware contract before the solution, and every testbench checks itself.
Five modules — combinational logic to verified interfaces
Combinational RTL Design
Gates, selection, decoding and arithmetic — complete assignments, explicit numeric_std conversions, and no inferred latches.
Sequential Logic
Flip-flops, registers and counters — rising_edge, reset semantics stated and tested, and the difference a clock edge makes.
FSM & Control Design
Enumerated-type state machines that detect, sequence, time and handshake — with output timing verified, not assumed.
Datapath & Memory
Generic-driven arithmetic, shifters, register files, RAM and FIFO — then a UART transmitter checked bit by bit against the frame.
Advanced RTL & Verification
Receivers, PWM, SPI and clock-domain crossing, closing with boundary-condition verification and an automated regression.
Each lab: problem statement, specification, explanation, RTL, self-checking testbench, simulation procedure and results, waveform walkthrough, common mistakes, checklist and takeaway.
All 30 labs
Search and filter the full curriculum. Titles, previews and metadata are free to browse — full lab content requires the labs package.
Module 1Combinational RTL Design
Gates, selection, decoding and arithmetic — complete assignments, explicit numeric_std conversions, and no inferred latches.
- Lab 1Combinational RTL Design
Basic Logic Gates
Describe AND, OR, NOT, NAND, NOR, XOR and XNOR as concurrent signal assignments and prove all seven against an exhaustive truth table.
Beginner·30 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 2Combinational RTL Design
2:1 and 4:1 Multiplexer
Build a 2:1 and a 4:1 multiplexer with selected and conditional assignments, and see why a complete choice list matters.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 3Combinational RTL Design
2-to-4 Decoder with Enable
Decode two address bits into one-hot outputs gated by an enable, and verify the outputs are all-zero whenever the enable is low.
Beginner·30 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 4Combinational RTL Design
Priority Encoder
Encode the highest-priority active request into a binary index with a valid flag, and prove the priority order over every input.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 5Combinational RTL Design
Half Adder and Full Adder
Derive sum and carry from first principles, compose a full adder from two half adders, and check against integer arithmetic.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 6Combinational RTL Design
4-bit Arithmetic Logic Unit
Implement add, subtract and logic operations with carry, zero and overflow flags using numeric_std signed and unsigned arithmetic.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid
Module 2Sequential Logic
Flip-flops, registers and counters — rising_edge, reset semantics stated and tested, and the difference a clock edge makes.
- Lab 7Sequential Logic
D Flip-Flop with Asynchronous Reset
Write a flip-flop whose reset acts immediately, independent of the clock, and prove that timing in simulation.
Beginner·30 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 8Sequential Logic
D Flip-Flop with Synchronous Reset
Write a flip-flop whose reset waits for the clock, and measure exactly how it differs from the asynchronous version.
Beginner·30 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 9Sequential Logic
Shift Register with Enable
Build a serial-in parallel-out shift register that advances only when enabled, and check every bit position over time.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 10Sequential Logic
4-bit Up/Down Counter
Count up or down under control with enable and synchronous load, and verify wrap-around in both directions.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 11Sequential Logic
Mod-10 Counter
Count 0 to 9 with a terminal-count output, recover from illegal values, and cascade two counters into a decade pair.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 12Sequential Logic
Universal Shift Register
Hold, shift left, shift right or parallel-load under a mode select, and verify every mode against a software model.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid
Module 3FSM & Control Design
Enumerated-type state machines that detect, sequence, time and handshake — with output timing verified, not assumed.
- Lab 13FSM & Control Design
Moore Sequence Detector
Detect an overlapping serial pattern with an enumerated-type Moore machine whose output depends on state alone.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 14FSM & Control Design
Mealy Sequence Detector
Detect the same pattern with a Mealy machine and measure the one-clock lead its output has over the Moore version.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 15FSM & Control Design
Traffic Light Controller
Sequence two road directions through timed phases with a single down-counter, and verify no conflicting greens ever occur.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 16FSM & Control Design
Vending Machine Controller
Accumulate coins toward a price, vend and return change, and verify credit is conserved on every path.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 17FSM & Control Design
Programmable Timer
Load a terminal value, count with a prescaler, and support one-shot and auto-reload modes with an exact expiry cycle.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 18FSM & Control Design
Request-Acknowledge Handshake Controller
Implement a four-phase req/ack handshake and verify its ordering rules hold under variable response delays.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid
Module 4Datapath & Memory
Generic-driven arithmetic, shifters, register files, RAM and FIFO — then a UART transmitter checked bit by bit against the frame.
- Lab 19Datapath & Memory
Parameterized N-bit Adder
Write one adder whose width is a generic, build it with a generate loop, and verify several widths from one testbench.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 20Datapath & Memory
Barrel Shifter
Shift or rotate a word by any amount in one cycle using log2 stages, and verify every amount against shift_left and rotate_left.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 21Datapath & Memory
Register File with Two Read Ports
Build a register file with one synchronous write and two asynchronous reads, and define what a same-cycle read returns.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 22Datapath & Memory
Single-Port Synchronous RAM
Infer a block-RAM-style single-port memory with registered read data, and verify its one-cycle read latency.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 23Datapath & Memory
Synchronous FIFO
Build a FIFO with full, empty and count from wrapped pointers, and check it against a queue model under simultaneous read and write.
Advanced·60 min·Testbench·2 challengesAdvancedPublishedPaid - Lab 24Datapath & Memory
UART Transmitter
Serialise bytes into 8N1 frames at a generic baud divisor, and verify every bit's level and duration on the line.
Advanced·60 min·Testbench·2 challengesAdvancedPublishedPaid
Module 5Advanced RTL & Verification
Receivers, PWM, SPI and clock-domain crossing, closing with boundary-condition verification and an automated regression.
- Lab 25Advanced RTL & Verification
UART Receiver with Framing Checks
Recover bytes by mid-bit sampling, reject false starts, flag framing errors, and verify against a behavioural transmitter.
Advanced·60 min·Testbench·2 challengesAdvancedPublishedPaid - Lab 26Advanced RTL & Verification
PWM Generator
Generate a PWM output with a glitch-free duty update at the period boundary, and measure duty cycle from the waveform.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 27Advanced RTL & Verification
SPI Master Controller
Drive a mode-0 SPI transfer with chip select, clock and MOSI, capture MISO, and verify both directions with a slave model.
Advanced·60 min·Testbench·2 challengesAdvancedPublishedPaid - Lab 28Advanced RTL & Verification
Clock-Domain Crossing Pulse Synchronizer
Move a single-cycle pulse between unrelated clocks with a toggle synchroniser, and state precisely what simulation cannot prove.
Advanced·55 min·Testbench·2 challengesAdvancedPublishedPaid - Lab 29Advanced RTL & Verification
FIFO Overflow and Underflow Verification
Drive a FIFO past full and below empty, define the safe behaviour, and prove each boundary with dedicated checks.
Advanced·55 min·Testbench·2 challengesAdvancedPublishedPaid - Lab 30Advanced RTL & Verification
Parameterized ALU with Automated Regression Tests
Build a generic-width ALU and a regression that runs directed and randomised vectors at several widths against one reference model.
Advanced·60 min·Testbench·2 challengesAdvancedPublishedPaid