While Loop in Verilog — Condition Loops & the Static-Bound Requirement

Chapter 14 · Section 14.6.2 · Behavioural Modeling

1. The Engineering Problem

A while loop repeats on a condition — and whether it synthesizes depends entirely on whether that condition is statically bounded:

A while loop synthesizes only if it is statically bounded (the condition reduces to a fixed iteration count at elaboration). A data-dependent while is testbench-only.

2. Mental Model — Loop While a Condition Holds; Static to Synthesize

3. The While Loop

   // statically bounded (synthesizable) — equivalent to a for loop:
   i = 0;
   while (i < WIDTH) begin           // WIDTH static → bounded
       y[i] = a[i] & b[i];
       i = i + 1;
   end
 
   // data-dependent (testbench-only) — iterate until a runtime condition:
   while (!done) begin
       drive_stimulus();
       @(posedge clk);
   end

The first while counts a loop variable to a static limit — it unrolls like a for (and is usually written as a for). The second loops on a runtime condition (!done) — testbench-only, since the iteration count depends on simulation behaviour. A while needs its body to make progress toward the condition, or it loops forever.

4. Common Mistakes

1. Data-dependent while in synthesizable design — not synthesizable; use for with a static bound (§2).
2. No progress toward the condition — an infinite loop (a simulation hang).
3. Using while where for is clearer — count loops read better as for (§3).

5. Debugging Lab

task wait_for_grant;
  begin
      // Intent: hold here until the bus grant arrives, then proceed.
      while (grant == 1'b0) begin
          // ... no clock advance, no event, nothing that lets time pass ...
          checks = checks + 1;          // spins, but time never moves
      end
      do_transfer();
  end
endtask

// 'grant' is driven by another part of the design that only updates on a
// clock edge. But this while body contains NO timing control (no @(posedge
// clk), no #delay, no wait) — so the loop spins in a SINGLE simulation
// instant, never yielding control. Time cannot advance, so the clock never
// ticks, so 'grant' can never become 1. The loop condition is therefore
// permanently false: the simulation HANGS (or appears frozen at one time),
// and do_transfer() is never reached.

task wait_for_grant;
  begin
      // Option A — advance a clock each iteration so 'grant' can update:
      while (grant == 1'b0)
          @(posedge clk);               // yields time; clock ticks; grant moves
      do_transfer();
  end
endtask

// Option B — a level wait, which suspends until the condition holds:
//    wait (grant);  do_transfer();
//
// Either way the loop must let simulation time pass so the awaited signal can
// actually change. A while that polls a signal must contain a timing control;
// otherwise it deadlocks the simulation. (For a pure level condition, prefer
// wait — 14.4.3.)

6. Interview Q&A

7. Exercises

Exercise 1 — Synthesizable?

Which synthesize: (a) while (i < 8) ... with i counting up; (b) while (!ready) ... with ready a runtime signal?

Exercise 2 — Convert to for

Rewrite the statically-bounded while in §3 as a for loop.

8. Summary

The while loop repeats on a condition:

• Synthesizable only if statically bounded (condition reduces to a fixed count); data-dependent while is testbench-only.
• Prefer for for synthesizable iteration (explicit static bound); use while in testbenches.
• Must make progress toward the condition, or it loops forever.

The next sub-topic is the fixed-count loop: Chapter 14.6.3 Repeat Loop drills repeat — repeating a body a fixed number of times.

Related Tutorials

• For Loop — Chapter 14.6.1; the preferred synthesizable count loop.
• Loops — Chapter 14.6; the loop overview and unrolling concept.
• Level-Sensitive Timing Controls — Chapter 14.4.3; wait, a testbench alternative to a data-dependent while.
• Testbench Creation Techniques — Chapter 9.5; where data-dependent loops are used.