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Verilog · Chapter 14.6.2 · Behavioural Modeling

While Loop in Verilog — Condition Loops & the Static-Bound Requirement

The while loop repeats its body as long as a condition is true, making it a condition-controlled loop in contrast to the count-controlled for loop. Its synthesizability follows the same unrolling rule as every loop. A while loop synthesizes only if it is statically bounded, meaning the condition reduces to a fixed iteration count known at elaboration, such as a loop variable counting up to a constant. A while loop driven by a runtime condition, one that waits while a signal holds or iterates an input-dependent number of times, cannot be unrolled and is testbench-only. In practice, synthesizable iteration is almost always written with for, whose static bound is explicit, while while loops appear mainly in testbenches where data-dependent looping is fine. This page drills the while loop and its static-bound requirement.

Foundation9 min readVerilogwhile loopConditionTestbench

Chapter 14 · Section 14.6.2 · Behavioural Modeling

1. The Engineering Problem

A while loop repeats on a condition — and whether it synthesizes depends entirely on whether that condition is statically bounded:

A while loop synthesizes only if it is statically bounded (the condition reduces to a fixed iteration count at elaboration). A data-dependent while is testbench-only.

2. Mental Model — Loop While a Condition Holds; Static to Synthesize

3. The While Loop

while.v
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Snippet
   // statically bounded (synthesizable) — equivalent to a for loop:
   i = 0;
   while (i < WIDTH) begin           // WIDTH static → bounded
       y[i] = a[i] & b[i];
       i = i + 1;
   end
 
   // data-dependent (testbench-only) — iterate until a runtime condition:
   while (!done) begin
       drive_stimulus();
       @(posedge clk);
   end

The first while counts a loop variable to a static limit — it unrolls like a for (and is usually written as a for). The second loops on a runtime condition (!done) — testbench-only, since the iteration count depends on simulation behaviour. A while needs its body to make progress toward the condition, or it loops forever.

4. Common Mistakes

  1. Data-dependent while in synthesizable design — not synthesizable; use for with a static bound (§2).
  2. No progress toward the condition — an infinite loop (a simulation hang).
  3. Using while where for is clearer — count loops read better as for (§3).

5. Debugging Lab

One while-loop debug post-mortem

6. Interview Q&A

7. Exercises

Exercise 1 — Synthesizable?

Which synthesize: (a) while (i < 8) ... with i counting up; (b) while (!ready) ... with ready a runtime signal?

Exercise 2 — Convert to for

Rewrite the statically-bounded while in §3 as a for loop.

8. Summary

The while loop repeats on a condition:

  • Synthesizable only if statically bounded (condition reduces to a fixed count); data-dependent while is testbench-only.
  • Prefer for for synthesizable iteration (explicit static bound); use while in testbenches.
  • Must make progress toward the condition, or it loops forever.

The next sub-topic is the fixed-count loop: Chapter 14.6.3 Repeat Loop drills repeat — repeating a body a fixed number of times.