if/else Statements in Verilog — Priority Branching & Latch Avoidance

Chapter 14 · Section 14.5.1 · Behavioural Modeling

1. The Engineering Problem

if/else is the most-used branch, and it carries two facts every RTL engineer must hold: it is a priority structure, and in combinational logic it must be complete.

if/else if/else checks conditions in order — the first true one wins (priority) — and a combinational if without an else infers a latch.

This page drills the priority semantics and the latch-avoidance discipline for if/else.

2. Mental Model — First True Condition Wins

3. Priority Branching

   always @(*)
       if      (irq)   action = SERVICE_IRQ;   // highest priority
       else if (busy)  action = WAIT;
       else if (ready) action = PROCEED;
       else            action = IDLE;           // else → complete (no latch)

irq is checked first; busy only if irq is false; and so on. The first true condition wins, so this is a priority encoder of actions — exactly when if/else is the right choice (the conditions have a natural precedence). The final else ensures action is always assigned.

Visual A — an if/else chain is a cascade of muxes (priority is structural)

4. Nesting and Grouping

if statements nest, and multiple statements per branch need begin...end (14.2):

   always @(*)
       if (mode) begin                  // begin...end for >1 statement
           y = a;
           valid = 1;
       end else begin
           y = b;
           valid = 0;
       end
 
   // nested if for compound conditions:
   always @(*)
       if (en)
           if (sel) y = a;              // inner if
           else     y = b;
       else y = 0;

Remember the dangling-else and missing-begin...end traps from 14.2 — wrap multi-statement branches in begin...end, and be explicit about which if an else pairs with.

5. Latch Avoidance for if

A combinational if must assign every output on both the true and false paths:

   // LATCH — y unassigned when en=0:
   always @(*) if (en) y = d;
 
   // FIX — else:
   always @(*) if (en) y = d; else y = 0;
 
   // FIX — default first:
   always @(*) begin
       y = 0;
       if (en) y = d;
   end

The default-first pattern scales to complex branching: assign defaults at the top, override in branches, so no path leaves an output unassigned. (Sequential @(posedge clk) blocks intentionally hold, so an if without else there is a register that holds — fine; this latch rule is for combinational blocks.)

Visual B — completeness, and the latch from a missing else

6. Common Mistakes

1. Missing else in combinational if — infers a latch; complete it (§5, DebugLab 1).
2. Using if/else where case is clearer — value selection reads better as case (14.5.2).
3. Missing begin...end — a statement escapes the branch (14.2).
4. Dangling else — an else pairs with the nearest unmatched if; be explicit (§4).

7. Debugging Lab

8. Interview Q&A

9. Exercises

Exercise 1 — Priority order

For if (a) y=1; else if (b) y=2; else y=3;, which value does y get when both a and b are true, and why?

Exercise 2 — Spot the latch

Why does always @(*) if (sel) y = d; infer a latch, and what are two fixes?

Exercise 3 — Write a priority encoder

Write a combinational if/else that outputs the index (2-bit) of the highest-priority set bit among r[3:0] (r[3] highest), with a complete else.

10. Summary

The if/else statement is priority branching:

• Priority — first true condition wins; synthesizes to a priority-mux cascade; textual order is priority order.
• Nesting and grouping — nest for compound conditions; begin...end for multi-statement branches.
• Latch avoidance — a combinational if needs an else (or default-first) so every path assigns every output; otherwise a latch is inferred.

The next sub-topic is the parallel branch: Chapter 14.5.2 Case Statements drills case/casez/casex — value selection, default for latch avoidance, and the casex x-matching hazard.

Related Tutorials

• Multiway Branching — Chapter 14.5; the branching overview and latch discipline.
• Conditional Operator — Chapter 10.11; the ternary's priority-chain parallel.
• Sequential & Parallel Blocks — Chapter 14.2; begin...end grouping for branches.
• Case Statements — Chapter 14.5.2; the parallel branching alternative.
• Generate if — Chapter 14.7.2; the elaboration-time counterpart — a runtime if builds a mux, a generate if includes/excludes structure.