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Verilog · Chapter 14.6.3 · Behavioural Modeling

Repeat Loop in Verilog — Fixed-Count Repetition

The repeat loop runs its body a fixed number of times, with no index variable and no condition, just a count. With a static count it is synthesizable and unrolls into that many copies of the body, like a for loop without the index bookkeeping. Its most common use, though, is in testbenches, where waiting on a repeated clock edge is a clean way to advance a fixed number of cycles without a manual counter. That single line reads clearly and keeps stimulus code short. This page walks through the repeat loop, its fixed-count semantics, synthesizable unrolling with a static count, and the canonical testbench pattern of counting clock edges so your simulation advances exactly as many cycles as you intend.

Foundation8 min readVerilogrepeat loopFixed CountTestbenchClock Edges

Chapter 14 · Section 14.6.3 · Behavioural Modeling

1. The Engineering Problem

repeat is the simplest loop — run a body a fixed number of times, no index, no condition:

repeat (N) runs its body exactly N times. A static N is synthesizable (unrolls); the common use is counting clock edges in testbenches.

2. Mental Model — Run the Body N Times

3. The Repeat Loop

repeat.v
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Snippet
   // synthesizable — fixed count unrolls:
   repeat (4) shift_reg = {shift_reg[6:0], 1'b0};   // shift left 4 times (unrolls)
 
   // testbench — count clock edges (the common use):
   repeat (10) @(posedge clk);          // wait exactly 10 clock edges
   $display("10 cycles elapsed");
 
   // testbench — apply N stimulus items:
   repeat (N) begin
       data = $random;
       @(posedge clk);
   end

repeat (N) runs the body N times. With a static N and combinational/synthesizable body it unrolls; combined with @(posedge clk) it counts edges (the most common use, in testbenches). Unlike for, there is no index — use for when you need the iteration number.

4. Common Mistakes

  1. Runtime-N repeat in synthesizable design — a runtime count can't unroll (like any loop, §2).
  2. Needing the index — repeat has none; use for (§3).
  3. repeat without @(posedge clk) for cycle counting — to count cycles, the body must consume a clock edge (§3).

5. Interview Q&A

6. Exercises

Exercise 1 — Count cycles

Write a testbench fragment that waits 8 clock edges using repeat.

Exercise 2 — repeat vs for

When would you use repeat instead of for, and when not?

7. Summary

The repeat loop is fixed-count repetition:

  • repeat (N) runs the body exactly N times; no index, no condition.
  • Static N synthesizes (unrolls); the common use is counting clock edges in testbenches (repeat (N) @(posedge clk)).
  • Use for when you need the iteration index.

The next sub-topic is the infinite loop: Chapter 14.6.4 Forever Loop drills forever — the testbench-only infinite loop used for clock generation.