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Verilog · Chapter 14.6.4 · Behavioural Modeling

Forever Loop in Verilog — Infinite Loops & Clock Generation

The forever loop runs its body indefinitely and never terminates on its own. That makes it a purely testbench and simulation construct, because it has no synthesizable hardware meaning. Its canonical use is clock generation, where a single line toggles a clock every few time units for the whole run. A forever loop must contain a timing control, either a delay or an event, so that simulation time advances on each pass. Without one, it becomes a zero-delay infinite loop that hangs the simulator at time zero. This lesson drills the loop, its clock-generation use, the rule that time must advance each pass, and why it never appears in synthesizable design. It also shows why the testbench must eventually call a finish task to end the run.

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Chapter 14 · Section 14.6.4 · Behavioural Modeling

1. The Engineering Problem

forever runs indefinitely — useful for a clock, dangerous without a timing control:

forever is an infinite, testbench-only loop (clock generation, continuous stimulus). It must contain a timing control (# or @) so time advances, or it hangs the simulation.

2. Mental Model — Run Forever; Advance Time Each Pass

3. The Forever Loop

forever.v
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Snippet
   // clock generation — the canonical use:
   initial begin
       clk = 0;
       forever #5 clk = ~clk;        // toggle every 5 units → 10-unit period
   end
 
   // continuous monitoring / stimulus:
   initial forever @(posedge clk) $display("cycle at t=%0t", $time);

forever #5 clk = ~clk; is the standard clock generator (equivalent to always #5 clk = ~clk;). The #5 advances time each pass; without it the loop would spin at time 0 forever, hanging the simulation. Because forever never ends, the testbench must call $finish to terminate the run (Chapter 8.5).

4. Common Mistakes

  1. forever with no timing control — a zero-delay loop that hangs the simulation (§2, DebugLab 1).
  2. forever in synthesizable design — not synthesizable; testbench-only (§2).
  3. No $finish — forever keeps the simulation alive; the testbench must terminate it (8.5).

5. Debugging Lab

One forever-loop debug post-mortem

6. Interview Q&A

7. Exercises

Exercise 1 — Generate a clock

Write a forever-based clock generator with a 20-unit period.

Exercise 2 — Spot the hang

Why does forever a = ~a; (with no delay) hang the simulation?

8. Summary

The forever loop is an infinite, testbench-only loop:

  • Runs indefinitely — never terminates; not synthesizable.
  • Clock generation — forever #5 clk = ~clk; is the canonical use.
  • Must advance time — a # delay or @ event inside, or it hangs the simulation.
  • Needs $finish — the testbench terminates the run (8.5).

The last loop sub-topic combines techniques: Chapter 14.6.5 Loops Advanced Techniques covers nested loops, disable for break/continue, and common loop patterns.