Forever Loop in Verilog — Infinite Loops & Clock Generation

Chapter 14 · Section 14.6.4 · Behavioural Modeling

1. The Engineering Problem

forever runs indefinitely — useful for a clock, dangerous without a timing control:

forever is an infinite, testbench-only loop (clock generation, continuous stimulus). It must contain a timing control (# or @) so time advances, or it hangs the simulation.

2. Mental Model — Run Forever; Advance Time Each Pass

3. The Forever Loop

   // clock generation — the canonical use:
   initial begin
       clk = 0;
       forever #5 clk = ~clk;        // toggle every 5 units → 10-unit period
   end

   // continuous monitoring / stimulus:
   initial forever @(posedge clk) $display("cycle at t=%0t", $time);

forever #5 clk = ~clk; is the standard clock generator (equivalent to always #5 clk = ~clk;). The #5 advances time each pass; without it the loop would spin at time 0 forever, hanging the simulation. Because forever never ends, the testbench must call $finish to terminate the run (Chapter 8.5).

4. Common Mistakes

1. forever with no timing control — a zero-delay loop that hangs the simulation (§2, DebugLab 1).
2. forever in synthesizable design — not synthesizable; testbench-only (§2).
3. No $finish — forever keeps the simulation alive; the testbench must terminate it (8.5).

5. Debugging Lab

initial begin
  count = 0;
  forever count = count + 1;     // BUG: no timing control
end

// The loop body has no # delay or @ event, so it executes infinitely at
// time 0 — simulation time never advances, the simulator spins forever (or
// errors on an iteration limit). Nothing else in the simulation runs.

initial begin
  count = 0;
  forever @(posedge clk) count = count + 1;   // advances each clock edge
end

// Now each pass waits for a clock edge, so simulation time advances and the
// rest of the simulation runs. (And the testbench must $finish eventually.)

6. Interview Q&A

7. Exercises

Exercise 1 — Generate a clock

Write a forever-based clock generator with a 20-unit period.

Exercise 2 — Spot the hang

Why does forever a = ~a; (with no delay) hang the simulation?

8. Summary

The forever loop is an infinite, testbench-only loop:

• Runs indefinitely — never terminates; not synthesizable.
• Clock generation — forever #5 clk = ~clk; is the canonical use.
• Must advance time — a # delay or @ event inside, or it hangs the simulation.
• Needs $finish — the testbench terminates the run (8.5).

The last loop sub-topic combines techniques: Chapter 14.6.5 Loops Advanced Techniques covers nested loops, disable for break/continue, and common loop patterns.

Related Tutorials

• Delay-Based Timing Controls — Chapter 14.4.1; the # delay that advances forever.
• Loops — Chapter 14.6; the loop overview.
• Simulation Control — Chapter 8.5; the $finish that ends a forever-driven run.
• Testbench Creation Techniques — Chapter 9.5; clock generation.