Advanced Timing Techniques in Verilog — Intra-Assignment Delays & Named Events

Chapter 14 · Section 14.4.4 · Behavioural Modeling

1. The Engineering Problem

Sophisticated testbenches need finer timing control than a single delay or event — precise sampling moments, synchronization between concurrent stimulus processes, multi-step waits. The advanced techniques combine the basic timing controls:

Intra-assignment delays separate sampling from application; named events synchronize concurrent processes; combined controls express multi-step timing. These are the testbench patterns built on the basic timing controls.

This page drills them as the advanced layer of procedural timing.

2. Intra-Assignment Delays — Sample Now, Apply Later

An intra-assignment delay puts the timing control after the =, separating when the right-hand side is read from when the assignment applies:

   a = #5 b;          // sample b NOW, apply to a after 5 time units
   q = @(posedge clk) d;   // sample d NOW, apply to q at the next clock edge
   r = @(done) x;     // sample x NOW, apply to r when 'done' fires

• a = #5 b; — b is read immediately; a updates 5 units later (even if b changes meanwhile, a gets the old b).
• q = @(posedge clk) d; — d is sampled now, applied at the next clock edge — a way to capture a value and apply it later.
• Contrast #5 a = b; (inter-statement), which waits then samples b. The intra form samples now.

Intra-assignment delays model timing where the value is fixed at one moment but the update happens at another — a testbench/sim technique.

3. Named Events — Synchronize Concurrent Processes

A named event decouples a triggering process from a waiting one:

   event data_ready;                  // declare
 
   // producer process:
   initial begin
       prepare_data();
       -> data_ready;                 // trigger the event
   end
 
   // consumer process:
   initial begin
       @(data_ready);                 // wait for the trigger
       consume_data();
   end

• event name; declares; -> name; triggers; @(name) waits.
• A named event carries no data — it is a pure synchronization signal. The producer fires it; one or more consumers waiting on @(name) proceed.
• Used to coordinate concurrent testbench processes (a generator signals a driver, a monitor signals a scoreboard) without shared flags or polling.

Visual A — named-event synchronization

4. Combining Timing Controls

Timing controls combine for multi-step synchronization:

   @(posedge clk) #2 sample = bus;    // at the edge, then 2 units later, sample
   wait(ready) @(posedge clk) data = bus;  // wait for ready, then the next edge
   repeat (3) @(posedge clk);         // wait 3 clock edges (with a loop, 14.6)

• @(posedge clk) #2 ... — wait for the edge, then an additional delay (e.g. to sample past clock-to-q).
• wait(ready) @(posedge clk) ... — wait for a level, then synchronize to the next edge.
• repeat (N) @(posedge clk); — wait N clock edges (combining a loop with event control, common in testbenches).

These compositions express the precise, multi-step timing real testbench protocols need. All simulation/testbench techniques.

5. Common Mistakes

1. Confusing intra- and inter-assignment delay — a = #5 b samples now; #5 a = b samples later (§2).
2. Expecting a named event to carry data — it is a pure trigger, no value (§3).
3. Using these in synthesizable design — they are testbench/sim techniques (§1).
4. Missing trigger/wait pairing — a consumer @(event) blocks forever if no producer -> event (§3).

6. Interview Q&A

7. Exercises

Exercise 1 — Intra vs inter

For b = 3; a = #5 b; b = 7; (with b = 7 before t+5), what does a get? How would #5 a = b; differ?

Exercise 2 — Named event

Write a producer and consumer synchronized by a named event go.

Exercise 3 — Combine controls

Write a testbench line that waits for ready, then samples bus at the next clock edge.

8. Summary

Advanced timing techniques combine the basic controls:

• Intra-assignment delays — a = #5 b; / q = @(posedge clk) d;: sample the RHS now, apply later.
• Named events — event e; -> e; @(e);: pure synchronization between concurrent processes.
• Combined controls — @(posedge clk) #2 ..., wait(c) @(posedge clk) ..., repeat(N) @(posedge clk): multi-step timing.
• All testbench/simulation techniques.

Timing controls complete

This closes Chapter 14.4 Timing Controls — the delay (#), event (@), and level (wait) controls, plus the advanced combinations. The synthesizable one is the @ event control (the trigger of all logic); the rest are testbench/simulation tools.

The chapter now turns to decision logic: Chapter 14.5 Multiway Branching drills if/else and case — the branching constructs of behavioural logic — including the latch-avoidance discipline previewed in 14.1.

Related Tutorials

• Level-Sensitive Timing Controls — Chapter 14.4.3; wait, combined with these techniques.
• Event-Based Timing Controls — Chapter 14.4.2; the @ event control and named events.
• Delay-Based Timing Controls — Chapter 14.4.1; the # delays used in intra-assignment form.
• Testbench Creation Techniques — Chapter 9.5; where these patterns are used.