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Verilog · Chapter 14.4.1 · Behavioural Modeling

Delay-Based Timing Controls in Verilog — The # Delay

The hash delay control pauses a procedural statement for a fixed number of time units before it runs. It is how a testbench paces stimulus and how a clock generator toggles its signal on a steady beat. There are two forms. An inter-statement delay waits the given number of units and then executes the statement. An intra-assignment delay evaluates the right-hand side immediately but applies the result only after the delay passes. Both forms are simulation-only, because synthesis ignores them entirely; real hardware timing comes from the cell library and the physical implementation, not from numbers in the source. So these delays belong in testbenches and simple timing models, never in synthesizable design logic. This lesson drills both forms and their common uses.

Foundation11 min readVerilogDelayTimingTestbenchSimulation

Chapter 14 · Section 14.4.1 · Behavioural Modeling

1. The Engineering Problem

A testbench needs to time things — toggle a clock every 5 units, hold reset for 20, apply stimulus at specific moments. The delay control # provides this, with one rule that must be clear:

The # delay paces statements in time, and it is simulation-only — synthesis ignores it. Delays belong in testbenches, never in synthesizable design logic.

This page drills the # delay — its inter-statement and intra-assignment forms — and its testbench uses.

2. Mental Model — # Pauses Time in Simulation

3. Inter-Statement Delay

The common form — wait, then execute:

inter-statement.v
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Snippet
   initial begin
       a = 0;
       #10 a = 1;        // wait 10, then a = 1   (a = 1 at t = 10)
       #5  a = 0;        // wait 5 more, then a = 0 (a = 0 at t = 15)
   end

The delay precedes the statement; in a sequential begin...end block, delays accumulate (14.2). This is how stimulus is paced — each # advances time before the next assignment.

4. Intra-Assignment Delay

The delay can sit inside an assignment, after the =:

intra-assignment.v
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Snippet
   a = #10 b;            // evaluate b NOW, assign to a after 10 time units
   // vs
   #10 a = b;            // wait 10, THEN evaluate b and assign
  • Intra-assignment a = #10 b; — the right-hand side (b) is sampled immediately, but the update to a is deferred by 10 units. If b changes during the delay, a still gets the old b.
  • Inter-statement #10 a = b; — the whole statement waits 10 units, then samples b (whatever it is at t+10) and assigns.

The difference is when the right-hand side is read — now (intra) vs after the delay (inter). Intra-assignment delays are used to model specific sampling timing in testbenches (drilled further in 14.4.4).

5. Testbench Uses

The canonical # patterns in testbenches:

testbench-delays.v
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Snippet
   // clock generation — toggle every 5 units (10-unit period)
   always #5 clk = ~clk;
 
   // reset sequence — assert, hold, release
   initial begin
       rst_n = 0;
       #20 rst_n = 1;
   end
 
   // paced stimulus
   initial begin
       a = 8'h00; #10;
       a = 8'hFF; #10;
       $finish;
   end

Clock generation (always #5 clk = ~clk;), reset sequences, and paced stimulus are all # delays — the everyday testbench timing (Chapter 9.5). All simulation-only.

6. Common Mistakes

  1. # delay in synthesizable design logic — ignored by synthesis; testbench-only (§2, DebugLab 1).
  2. Confusing inter- and intra-assignment timing — a = #10 b reads b now; #10 a = b reads it after (§4).
  3. Expecting a delay to model real gate timing — real timing comes from the library (11.2).
  4. Free-running clock with no $finish — always #5 clk runs forever; the testbench needs $finish (8.5).

7. Debugging Lab

One delay-control debug post-mortem

8. Interview Q&A

9. Exercises

Exercise 1 — Predict the timing

For initial begin a=0; #10 a=1; #5 a=0; end, give the times a is 0 and 1.

Exercise 2 — Inter vs intra

For b = 5; a = #10 b; b = 9; (with the b = 9 happening before t+10), what value does a get and why?

Exercise 3 — Write the clock

Write a clock generator with a 20-unit period.

10. Summary

The # delay paces procedural statements in time:

  • Inter-statement #10 statement; — wait, then execute.
  • Intra-assignment a = #10 b; — sample the RHS now, assign after the delay.
  • Simulation-only — synthesis ignores it; real timing comes from the library.
  • Testbench home — clock generation, reset sequences, paced stimulus.

The next sub-topic is the synthesizable timing control: Chapter 14.4.2 Event Based Timing Controls drills the @ event control — edges, level sensitivity, and named events — the mechanism that triggers clocked and combinational logic.

  • Timing Controls — Chapter 14.4; the three timing controls.
  • Gate Delays — Chapter 11.2; the same simulation-only delay nature.
  • Testbench Creation Techniques — Chapter 9.5; clock generation and stimulus pacing with #.
  • [timescale](/verilog/timescale-directive) — Chapter 7.3; the time units #` delays are measured in.