Event-Based Timing Controls in Verilog — The @ Event Control

Chapter 14 · Section 14.4.2 · Behavioural Modeling

1. The Engineering Problem

Clocked logic must run on the clock edge; combinational logic must run on any input change. Both are expressed by the @ event control — the synthesizable timing mechanism:

The @ event control runs a statement on a signal event: an edge (@(posedge clk)) for sequential logic, or a level change (@(*)) for combinational. It is the synthesizable timing control — the trigger of every always block.

This page drills the @ event control's three forms — edge, level, and named events.

2. Mental Model — @ Fires on a Signal Event

3. Edge-Sensitive Events

@(posedge clk) / @(negedge clk) fire on clock (or reset) edges — the trigger of sequential logic:

   always @(posedge clk)              // rising clock edge
       q <= d;                        // a flip-flop
 
   always @(posedge clk or negedge rst_n)  // edge + async reset
       if (!rst_n) q <= 0;
       else        q <= d;

• posedge — a transition to 1 (0→1, x→1, z→1); negedge — a transition to 0.
• Multiple edges combine with or: @(posedge clk or negedge rst_n) triggers on either, the basis of synchronous logic with asynchronous reset.
• Edge-sensitive event control synthesizes to flip-flops — it is how all clocked state is built (14.1).

4. Level-Sensitive Events

@(*) or an explicit list fires on any change in the watched signals — the trigger of combinational logic:

   always @(*)                        // any change in signals read
       y = sel ? a : b;               // combinational mux
 
   always @(a, b, sel)                // explicit list (error-prone — prefer @*)
       y = sel ? a : b;

• @(*) (Verilog-2001) auto-watches every signal the block reads — the preferred combinational form (no incomplete-list bug, 14.1).
• @(a, b, sel) is an explicit list; legal but error-prone if incomplete (the sim/synth mismatch of 14.1).
• Level-sensitive event control synthesizes to combinational logic.

5. Named Events

A named event provides explicit, programmer-controlled synchronization:

   event done;                        // declare a named event
 
   // trigger it:
   -> done;                           // fire the event
 
   // wait for it:
   @(done) $display("done fired");    // block until 'done' is triggered

• event name; declares a named event; -> name; triggers it; @(name) waits for it.
• Named events synchronize concurrent processes (a producer triggers, a consumer waits) — mostly in testbenches. They carry no data (just the trigger). (Drilled further in 14.4.4.)

Visual A — the @ event control forms

6. Common Mistakes

1. Explicit incomplete level list — @(a or b) missing a read signal causes a sim/synth mismatch; use @(*) (§4, 14.1).
2. Wrong edge polarity — posedge for rising, negedge for falling (§3).
3. Confusing edge and level — edge → sequential, level → combinational (§2).
4. Using a named event where a signal edge is meant — named events are for explicit sync, not clocking (§5).

7. Debugging Lab

8. Interview Q&A

9. Exercises

Exercise 1 — Edge or level?

State whether each infers sequential or combinational logic: (a) @(posedge clk); (b) @(*); (c) @(a, b); (d) @(negedge clk).

Exercise 2 — Write the sensitivity

Write the event control for: (a) a flip-flop with active-low async reset; (b) a combinational block reading a, b, c.

Exercise 3 — Named event

Write the declaration, trigger, and wait for a named event start.

10. Summary

The @ event control is the synthesizable timing control:

• Edge — @(posedge clk) / @(negedge rst_n): triggers sequential logic (flip-flops); combine with or for clock + async reset.
• Level — @(*) (preferred) / @(a, b): triggers combinational logic.
• Named event — event e; -> e; @(e): explicit synchronization (mostly testbench).
• It is the sensitivity that decides comb vs seq inference (14.1).

The next sub-topic is a simulation-only control: Chapter 14.4.3 Level Sensitive Timing Controls drills wait — blocking a statement until a condition becomes true.

Related Tutorials

• always & initial Blocks — Chapter 14.1; the inference rule the event control drives.
• Timing Controls — Chapter 14.4; the three timing controls.
• Blocking & Non-Blocking Assignments — Chapter 14.3; the assignments in these triggered blocks.
• reg — Chapter 5.2.1; the registers edge events build.