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UVM Verification Labs
Lab 43of 50
UVM Foundations and Simulation Lifecycle5
Driver, Monitor, Sequencer and Agent5
Sequences, Constraints and Stimulus Control5
Configuration, Factory and Reusability5
Scoreboards, Reference Models and Data Integrity5
Functional Coverage and Coverage Closure5
Protocol Verification and Multi-Agent Environments5
Reset, Concurrency and Advanced UVM Communication5
Debugging, Robustness and Verification Quality5
Production-Style UVM Verification Projects5
UVM-43Debugging, Robustness and Verification QualityPublished
X/Z Contamination and Reset Assumptions
How do you detect and debug X/Z contamination, uninitialized DUT state and incorrect reset assumptions?
Expert~135 min
Concepts covered
- Four-state checks
- $isunknown
- Uninitialized state
This lab is part of UVM Verification Labs
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