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UVM Verification Labs
Lab 22of 50

  1. UVM Foundations and Simulation Lifecycle5

  2. Driver, Monitor, Sequencer and Agent5

  3. Sequences, Constraints and Stimulus Control5

  4. Configuration, Factory and Reusability5

  5. Scoreboards, Reference Models and Data Integrity5

  6. Functional Coverage and Coverage Closure5

  7. Protocol Verification and Multi-Agent Environments5

  8. Reset, Concurrency and Advanced UVM Communication5

  9. Debugging, Robustness and Verification Quality5

  10. Production-Style UVM Verification Projects5

UVM-22Scoreboards, Reference Models and Data IntegrityPublished

FIFO Verification with a Queue-Based Scoreboard

How do you verify a synchronous FIFO using separate input and output monitors and a queue-based scoreboard?

Intermediate~90 min
Concepts covered
  • Input / output monitors
  • Expected-data queue
  • Ordering check
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