Skip to content
VLSI Mentor
All UVM Verification labs
UVM Verification Labs
Lab 32of 50

  1. UVM Foundations and Simulation Lifecycle5

  2. Driver, Monitor, Sequencer and Agent5

  3. Sequences, Constraints and Stimulus Control5

  4. Configuration, Factory and Reusability5

  5. Scoreboards, Reference Models and Data Integrity5

  6. Functional Coverage and Coverage Closure5

  7. Protocol Verification and Multi-Agent Environments5

  8. Reset, Concurrency and Advanced UVM Communication5

  9. Debugging, Robustness and Verification Quality5

  10. Production-Style UVM Verification Projects5

UVM-32Protocol Verification and Multi-Agent EnvironmentsPublished

AHB-Lite Slave Under Wait States and Errors

How do you verify an AHB-Lite slave under wait states, back-to-back transfers and error responses?

Advanced~135 min
Concepts covered
  • HREADY wait states
  • Pipelined address / data
  • Two-cycle ERROR response
This lab is part of UVM Verification Labs

Unlock the complete lab with the UVM Verification Labs collection.

Back to all labs