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Lab 46of 50
UVM Foundations and Simulation Lifecycle5
Driver, Monitor, Sequencer and Agent5
Sequences, Constraints and Stimulus Control5
Configuration, Factory and Reusability5
Scoreboards, Reference Models and Data Integrity5
Functional Coverage and Coverage Closure5
Protocol Verification and Multi-Agent Environments5
Reset, Concurrency and Advanced UVM Communication5
Debugging, Robustness and Verification Quality5
Production-Style UVM Verification Projects5
UVM-46Production-Style UVM Verification ProjectsPublished
Reusable Environment for a Configurable FIFO
How do you architect a reusable UVM environment for a configurable FIFO supporting multiple depths and data widths?
Expert~180 min
Concepts covered
- Configurable depth / width
- Environment architecture
- Test layering
This lab is part of UVM Verification Labs
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