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UVM Verification Labs
Lab 34of 50
UVM Foundations and Simulation Lifecycle5
Driver, Monitor, Sequencer and Agent5
Sequences, Constraints and Stimulus Control5
Configuration, Factory and Reusability5
Scoreboards, Reference Models and Data Integrity5
Functional Coverage and Coverage Closure5
Protocol Verification and Multi-Agent Environments5
Reset, Concurrency and Advanced UVM Communication5
Debugging, Robustness and Verification Quality5
Production-Style UVM Verification Projects5
UVM-34Protocol Verification and Multi-Agent EnvironmentsPublished
Multi-Port Memory Controller with a Shared Scoreboard
How do you verify a multi-port memory controller using multiple UVM agents and a shared scoreboard?
Advanced~135 min
Concepts covered
- Multiple agent instances
- Shared scoreboard
- Port contention
This lab is part of UVM Verification Labs
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