All UVM Verification labs
UVM Verification Labs
Lab 23of 50
UVM Foundations and Simulation Lifecycle5
Driver, Monitor, Sequencer and Agent5
Sequences, Constraints and Stimulus Control5
Configuration, Factory and Reusability5
Scoreboards, Reference Models and Data Integrity5
Functional Coverage and Coverage Closure5
Protocol Verification and Multi-Agent Environments5
Reset, Concurrency and Advanced UVM Communication5
Debugging, Robustness and Verification Quality5
Production-Style UVM Verification Projects5
UVM-23Scoreboards, Reference Models and Data IntegrityPublished
Scoreboarding a Pipelined Arithmetic DUT
How do you verify a pipelined arithmetic DUT when input and output transactions have different timing?
Intermediate~105 min
Concepts covered
- Pipeline latency
- Expected-result queue
- uvm_tlm_analysis_fifo
This lab is part of UVM Verification Labs
Unlock the complete lab with the UVM Verification Labs collection.