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UVM Verification Labs.

Fifty UVM verification problems, from a first runnable testbench to plan-to-sign-off on a parameterized subsystem — drivers, monitors and agents, sequences, the factory, scoreboards, functional coverage, protocol environments, reset and concurrency, and debugging. UVM RAL is covered by its own collection, not this one.

50Labs
10Modules
50Published
Foundation → ExpertLevel
All 50 labs are published. One purchase covers the entire collection.
UVM Labs

Ten modules — foundations to sign-off

Module 1Foundation · 5 labs

UVM Foundations and Simulation Lifecycle

A first runnable testbench, transactions, the component tree, objections and reporting.

UVM-01 · UVM-02 · UVM-03 · UVM-04 · UVM-05

Module 2Foundation · 5 labs

Driver, Monitor, Sequencer and Agent

Pin-level driving and sampling, sequences, and a reusable active/passive agent.

UVM-06 · UVM-07 · UVM-08 · UVM-09 · UVM-10

Module 3Intermediate · 5 labs

Sequences, Constraints and Stimulus Control

Constrained-random and corner-case stimulus, sequence reuse, arbitration and virtual sequences.

UVM-11 · UVM-12 · UVM-13 · UVM-14 · UVM-15

Module 4Intermediate · 5 labs

Configuration, Factory and Reusability

config_db, type and instance overrides, parameterized agents and configuration debugging.

UVM-16 · UVM-17 · UVM-18 · UVM-19 · UVM-20

Module 5Intermediate · 5 labs

Scoreboards, Reference Models and Data Integrity

Reference models, in-order, pipelined and out-of-order checking, and error classification.

UVM-21 · UVM-22 · UVM-23 · UVM-24 · UVM-25

Module 6Advanced · 5 labs

Functional Coverage and Coverage Closure

Coverage models, cross coverage, unreachable bins, targeted closure and closure reporting.

UVM-26 · UVM-27 · UVM-28 · UVM-29 · UVM-30

Module 7Advanced · 5 labs

Protocol Verification and Multi-Agent Environments

APB, AHB-Lite and AXI4-Lite environments, multi-port memory and packet routing.

UVM-31 · UVM-32 · UVM-33 · UVM-34 · UVM-35

Module 8Advanced · 5 labs

Reset, Concurrency and Advanced UVM Communication

Reset during traffic, analysis fabric, concurrent stimulus under backpressure, clean shutdown.

UVM-36 · UVM-37 · UVM-38 · UVM-39 · UVM-40

Module 9Expert · 5 labs

Debugging, Robustness and Verification Quality

Sampling races, hangs, X/Z contamination, reproducible regressions and false failures.

UVM-41 · UVM-42 · UVM-43 · UVM-44 · UVM-45

Module 10Expert · 5 labs

Production-Style UVM Verification Projects

Five subsystem-scale environments, ending in plan-to-sign-off for a parameterized RTL subsystem.

UVM-46 · UVM-47 · UVM-48 · UVM-49 · UVM-50

Lab numbers are stable IDs (Lab 21 is UVM-21). UVM RAL is a separate collection.

All 50 labs

Search and filter the full curriculum. Titles, previews and metadata are free to browse — full lab content requires the labs package.

50 of 50
Module
Difficulty
Status

Module 1UVM Foundations and Simulation Lifecycle

A first runnable testbench, transactions, the component tree, objections and reporting.

5 labs · 5 published
  1. Lab 1
    UVM Foundations and Simulation Lifecycle

    Minimal UVM Testbench for an 8-bit ALU

    How do you construct and run a minimal UVM testbench to verify an 8-bit combinational ALU?

    Foundation·60 min·Testbench·1 challenge
    FoundationPublishedPaid
  2. Lab 2
    UVM Foundations and Simulation Lifecycle

    Reusable Transaction for a Register-Based DUT

    How do you create a reusable UVM transaction for a synchronous register-based DUT?

    Foundation·60 min·Testbench·1 challenge
    FoundationPublishedPaid
  3. Lab 3
    UVM Foundations and Simulation Lifecycle

    Component Hierarchy and Construction Order

    How do you build a UVM component hierarchy and verify its construction order?

    Foundation·60 min·Testbench·1 challenge
    FoundationPublishedPaid
  4. Lab 4
    UVM Foundations and Simulation Lifecycle

    Objections and Simulation Lifetime

    How do you control simulation lifetime and transaction execution using UVM objections?

    Foundation·60 min·Testbench·1 challenge
    FoundationPublishedPaid
  5. Lab 5
    UVM Foundations and Simulation Lifecycle

    Structured Reporting and Verbosity Control

    How do you implement structured UVM reporting and control message verbosity for a failing DUT?

    Foundation·60 min·Testbench·1 challenge
    FoundationPublishedPaid

Module 2Driver, Monitor, Sequencer and Agent

Pin-level driving and sampling, sequences, and a reusable active/passive agent.

5 labs · 5 published
  1. Lab 6
    Driver, Monitor, Sequencer and Agent

    Driver for a Ready/Valid Register Interface

    How do you implement a UVM driver for a ready/valid register interface?

    Foundation·75 min·Testbench·1 challenge
    FoundationPublishedPaid
  2. Lab 7
    Driver, Monitor, Sequencer and Agent

    Monitor That Reconstructs Transactions

    How do you create a UVM monitor that reconstructs transactions from pin-level activity?

    Foundation·75 min·Testbench·1 challenge
    FoundationPublishedPaid
  3. Lab 8
    Driver, Monitor, Sequencer and Agent

    Sequencer and Write/Read Sequence

    How do you implement a sequencer and sequence to generate valid write/read transactions?

    Foundation·75 min·Testbench·1 challenge
    FoundationPublishedPaid
  4. Lab 9
    Driver, Monitor, Sequencer and Agent

    Reusable Agent with Active and Passive Modes

    How do you assemble a reusable UVM agent with active and passive operating modes?

    Foundation·75 min·Testbench·1 challenge
    FoundationPublishedPaid
  5. Lab 10
    Driver, Monitor, Sequencer and Agent

    Connecting a Complete UVM Environment

    How do you connect driver, sequencer and monitor through a complete UVM environment?

    Foundation·75 min·Testbench·1 challenge
    FoundationPublishedPaid

Module 3Sequences, Constraints and Stimulus Control

Constrained-random and corner-case stimulus, sequence reuse, arbitration and virtual sequences.

5 labs · 5 published
  1. Lab 11
    Sequences, Constraints and Stimulus Control

    Constrained-Random Transactions for a Parameterized FIFO

    How do you generate constrained-random transactions for a parameterized FIFO?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  2. Lab 12
    Sequences, Constraints and Stimulus Control

    Directed, Random and Corner-Case FIFO Sequences

    How do you create directed, random and corner-case UVM sequences for FIFO overflow and underflow?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  3. Lab 13
    Sequences, Constraints and Stimulus Control

    Base and Derived Sequences for a Register Peripheral

    How do you build reusable base sequences and derived sequences for a register-based peripheral?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  4. Lab 14
    Sequences, Constraints and Stimulus Control

    Sequence Priorities, Locks and Grabs

    How do you coordinate multiple sequences with priorities, locks and grabs on a shared sequencer?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  5. Lab 15
    Sequences, Constraints and Stimulus Control

    Virtual Sequence Coordinating Two Agents

    How do you create a virtual sequence that coordinates two independent UVM agents?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid

Module 4Configuration, Factory and Reusability

config_db, type and instance overrides, parameterized agents and configuration debugging.

5 labs · 5 published
  1. Lab 16
    Configuration, Factory and Reusability

    Virtual Interfaces and Configuration Objects via config_db

    How do you pass virtual interfaces and configuration objects through uvm_config_db?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  2. Lab 17
    Configuration, Factory and Reusability

    Factory Type Override of a Driver

    How do you replace a default driver using a UVM factory type override without changing the environment?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  3. Lab 18
    Configuration, Factory and Reusability

    Instance Override in a Multi-Agent Testbench

    How do you use instance overrides to customize one agent in a multi-agent testbench?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  4. Lab 19
    Configuration, Factory and Reusability

    Parameterized Agent Across 8-bit and 32-bit Datapaths

    How do you parameterize and reuse a UVM agent across 8-bit and 32-bit datapath interfaces?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  5. Lab 20
    Configuration, Factory and Reusability

    Debugging Factory, Configuration and Interface Errors

    How do you debug incorrect factory overrides, configuration paths and missing virtual interfaces?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid

Module 5Scoreboards, Reference Models and Data Integrity

Reference models, in-order, pipelined and out-of-order checking, and error classification.

5 labs · 5 published
  1. Lab 21
    Scoreboards, Reference Models and Data Integrity

    ALU Scoreboard with a Reference Model

    How do you build a self-checking UVM scoreboard for an ALU with a reference model?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  2. Lab 22
    Scoreboards, Reference Models and Data Integrity

    FIFO Verification with a Queue-Based Scoreboard

    How do you verify a synchronous FIFO using separate input and output monitors and a queue-based scoreboard?

    Intermediate·90 min·Testbench·1 challenge
    IntermediatePublishedPaid
  3. Lab 23
    Scoreboards, Reference Models and Data Integrity

    Scoreboarding a Pipelined Arithmetic DUT

    How do you verify a pipelined arithmetic DUT when input and output transactions have different timing?

    Intermediate·105 min·Testbench·1 challenge
    IntermediatePublishedPaid
  4. Lab 24
    Scoreboards, Reference Models and Data Integrity

    Out-of-Order Scoreboard Using Transaction IDs

    How do you build a scoreboard for out-of-order responses using transaction identifiers?

    Intermediate·105 min·Testbench·1 challenge
    IntermediatePublishedPaid
  5. Lab 25
    Scoreboards, Reference Models and Data Integrity

    Missing, Duplicate, Corrupted and Unexpected Transactions

    How do you detect missing, duplicated, corrupted and unexpected transactions in a UVM scoreboard?

    Intermediate·105 min·Testbench·1 challenge
    IntermediatePublishedPaid

Module 6Functional Coverage and Coverage Closure

Coverage models, cross coverage, unreachable bins, targeted closure and closure reporting.

5 labs · 5 published
  1. Lab 26
    Functional Coverage and Coverage Closure

    Transaction-Level Coverage for an ALU

    How do you implement transaction-level functional coverage for an ALU verification environment?

    Advanced·105 min·Testbench·1 challenge
    AdvancedPublishedPaid
  2. Lab 27
    Functional Coverage and Coverage Closure

    FIFO Cross Coverage of Operations, Occupancy and Reset

    How do you create cross coverage for FIFO operations, occupancy states and reset conditions?

    Advanced·105 min·Testbench·1 challenge
    AdvancedPublishedPaid
  3. Lab 28
    Functional Coverage and Coverage Closure

    Unreachable Bins versus Stimulus Gaps

    How do you identify unreachable coverage bins and distinguish stimulus gaps from DUT constraints?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid
  4. Lab 29
    Functional Coverage and Coverage Closure

    Targeted Sequences for Packet-Router Coverage Closure

    How do you develop targeted UVM sequences to close missing functional coverage on a packet router?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid
  5. Lab 30
    Functional Coverage and Coverage Closure

    Defensible Verification Closure Report

    How do you integrate coverage, assertions and scoreboard results into a defensible verification closure report?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid

Module 7Protocol Verification and Multi-Agent Environments

APB, AHB-Lite and AXI4-Lite environments, multi-port memory and packet routing.

5 labs · 5 published
  1. Lab 31
    Protocol Verification and Multi-Agent Environments

    APB Peripheral with Legal and Illegal Transfers

    How do you develop a complete UVM environment for an APB peripheral with legal and illegal bus transfers?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid
  2. Lab 32
    Protocol Verification and Multi-Agent Environments

    AHB-Lite Slave Under Wait States and Errors

    How do you verify an AHB-Lite slave under wait states, back-to-back transfers and error responses?

    Advanced·135 min·Testbench·1 challenge
    AdvancedPublishedPaid
  3. Lab 33
    Protocol Verification and Multi-Agent Environments

    AXI4-Lite Slave with Independent Channels

    How do you build a UVM environment for an AXI4-Lite slave with independent address and data channels?

    Advanced·135 min·Testbench·1 challenge
    AdvancedPublishedPaid
  4. Lab 34
    Protocol Verification and Multi-Agent Environments

    Multi-Port Memory Controller with a Shared Scoreboard

    How do you verify a multi-port memory controller using multiple UVM agents and a shared scoreboard?

    Advanced·135 min·Testbench·1 challenge
    AdvancedPublishedPaid
  5. Lab 35
    Protocol Verification and Multi-Agent Environments

    Multi-Port Packet Router with Backpressure

    How do you verify a packet router with multiple ingress and egress ports, routing rules and backpressure?

    Advanced·135 min·Testbench·1 challenge
    AdvancedPublishedPaid

Module 8Reset, Concurrency and Advanced UVM Communication

Reset during traffic, analysis fabric, concurrent stimulus under backpressure, clean shutdown.

5 labs · 5 published
  1. Lab 36
    Reset, Concurrency and Advanced UVM Communication

    Asynchronous Reset During Active Transactions

    How do you verify asynchronous reset assertion and synchronous reset release during active transactions?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid
  2. Lab 37
    Reset, Concurrency and Advanced UVM Communication

    Reset Interruption of Outstanding Requests

    How do you handle reset interruption of outstanding requests in drivers, monitors and scoreboards?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid
  3. Lab 38
    Reset, Concurrency and Advanced UVM Communication

    Analysis Ports, Exports and FIFOs

    How do you use analysis ports, analysis exports and analysis FIFOs to connect multiple UVM subscribers?

    Advanced·105 min·Testbench·1 challenge
    AdvancedPublishedPaid
  4. Lab 39
    Reset, Concurrency and Advanced UVM Communication

    Concurrent Producer and Consumer Sequences Under Backpressure

    How do you coordinate concurrent producer and consumer sequences under randomized backpressure?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid
  5. Lab 40
    Reset, Concurrency and Advanced UVM Communication

    Phase-Aware Shutdown

    How do you implement UVM phase-aware shutdown and ensure all accepted transactions are checked before test completion?

    Advanced·120 min·Testbench·1 challenge
    AdvancedPublishedPaid

Module 9Debugging, Robustness and Verification Quality

Sampling races, hangs, X/Z contamination, reproducible regressions and false failures.

5 labs · 5 published
  1. Lab 41
    Debugging, Robustness and Verification Quality

    Driver-Monitor Sampling Race

    How do you diagnose and eliminate a driver-monitor sampling race in a UVM testbench?

    Expert·135 min·Testbench·1 challenge
    ExpertPublishedPaid
  2. Lab 42
    Debugging, Robustness and Verification Quality

    Debugging a Hung Environment

    How do you debug a UVM environment that hangs because of blocked sequences or missing responses?

    Expert·135 min·Testbench·1 challenge
    ExpertPublishedPaid
  3. Lab 43
    Debugging, Robustness and Verification Quality

    X/Z Contamination and Reset Assumptions

    How do you detect and debug X/Z contamination, uninitialized DUT state and incorrect reset assumptions?

    Expert·135 min·Testbench·1 challenge
    ExpertPublishedPaid
  4. Lab 44
    Debugging, Robustness and Verification Quality

    Reproducible Random Regression and Failure Classification

    How do you build reproducible random regression tests with seed control and failure classification?

    Expert·135 min·Testbench·1 challenge
    ExpertPublishedPaid
  5. Lab 45
    Debugging, Robustness and Verification Quality

    False Scoreboard Failures

    How do you identify and correct false scoreboard failures caused by transaction aliasing, ordering or reference-model bugs?

    Expert·135 min·Testbench·1 challenge
    ExpertPublishedPaid

Module 10Production-Style UVM Verification Projects

Five subsystem-scale environments, ending in plan-to-sign-off for a parameterized RTL subsystem.

5 labs · 5 published
  1. Lab 46
    Production-Style UVM Verification Projects

    Reusable Environment for a Configurable FIFO

    How do you architect a reusable UVM environment for a configurable FIFO supporting multiple depths and data widths?

    Expert·180 min·Testbench·1 challenge
    ExpertPublishedPaid
  2. Lab 47
    Production-Style UVM Verification Projects

    APB-Controlled UART Environment

    How do you build a full UVM verification environment for an APB-controlled UART, including transmit and receive behavior?

    Expert·180 min·Testbench·1 challenge
    ExpertPublishedPaid
  3. Lab 48
    Production-Style UVM Verification Projects

    Multi-Channel DMA Engine Verification

    How do you verify a multi-channel DMA engine using coordinated bus agents, data integrity checks and error injection?

    Expert·210 min·Testbench·1 challenge
    ExpertPublishedPaid
  4. Lab 49
    Production-Style UVM Verification Projects

    Packet-Processing Subsystem Verification

    How do you verify a packet-processing subsystem with multiple agents, out-of-order completion and randomized backpressure?

    Expert·210 min·Testbench·1 challenge
    ExpertPublishedPaid
  5. Lab 50
    Production-Style UVM Verification Projects

    From Verification Plan to Sign-Off

    How do you take a complete UVM environment from verification planning to regression, coverage closure and sign-off for a parameterized RTL subsystem?

    Expert·240 min·Testbench·1 challenge
    ExpertPublishedPaid