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VLSI Mentor
150Total chapters
24Modules
150Chapters live
24 / 24Active modules

Electrical first principles

Why two wires, why open-drain, why pull-ups — the physics is taught before START/STOP, so the protocol mechanics finally make sense.

Interview-ready depth

A leveled interview module plus per-chapter interview weighting — open-drain, arbitration, clock stretching, and the misconceptions that trip candidates.

Design → verify → debug

Master/slave FSM RTL, open-drain modeling, SVA + a UVM agent, and waveform-based debugging for stuck buses and missing ACKs — the full loop.

I²C Complete Curriculum

Your Learning Roadmap

150 chapters · 24 modules — open-drain electricals, arbitration, clock stretching, and silicon-grade RTL.

150of 150 chapters live
100% complete
Module 1
Why I²C Exists
1.1Why Chips on a Board Need a Bus1.2From Parallel Buses to Two Wires1.3Where I²C Lives — Boards, SoCs and Real Devices1.4I²C vs SPI vs UART — Choosing a Board-Level Bus
Module 2
Electrical Bus & Open-Drain Design
2.1SDA and SCL — The Two-Wire Contract2.2Why Push-Pull Fails on a Shared Bus2.3Open-Drain Outputs — Drive Low, Release High2.4Pull-Up Resistors — Sizing, Rise Time and Bus Capacitance2.5Wired-AND — Many Drivers, One Line, No Contention2.6Real Bus Electrical Behavior — Edges, Levels and Level Shifting
Module 3
I²C Bus Architecture
3.1Master and Slave Roles (Controller and Target)3.2The Shared Bus — Many Targets, Sometimes Many Masters3.3Wiring a Real I²C Bus — Devices, Pull-Ups, Supplies and Segments3.4I²C Inside an SoC — Controller, Peripherals and the Software View
Module 4
Timing Fundamentals
4.1SCL Generation and the Bit Period4.2The Data-Valid Rule — SDA Stable While SCL Is High4.3Reading an I²C Timing Diagram
Module 5
START, STOP & Bus Framing
5.1Bus Idle and the Framing Primitives5.2The START Condition5.3The STOP Condition and Releasing the Bus5.4Repeated START — Holding the Bus Between Phases5.5START/STOP Timing and Malformed Framing
Module 6
Addressing
6.1The Address Byte — Seven Address Bits and the R/W Bit6.210-Bit Addressing6.3Reserved Addresses and the I²C Address Map6.4Address Allocation, Strapping, Conflicts and Bus Switches6.5Address Decoding Inside a Slave
Module 7
Byte Transfer & the ACK/NACK Cycle
7.1I²C Byte and Bit Transmission — MSB First, Nine Clocks7.2The ACK/NACK Cycle — What the Ninth Clock Proves7.3Who Acknowledges When — Slave ACK and Master ACK7.4The End-of-Transfer NACK7.5Reading a Complete I²C Frame
Module 8
Write Transactions
8.1The Write Transaction End to End8.2Master-Transmitter and Slave-Receiver Roles8.3Multi-Byte Writes — Timing, Throughput and Waveforms
Module 9
Read Transactions
9.1The Read Transaction End to End9.2Master-Receiver and Slave-Transmitter Roles9.3Multi-Byte Reads — ACK Policy, Timing and Waveforms
Module 10
Combined Transactions
10.1Write-Then-Read — The Register-Pointer Pattern10.2Repeated START in Practice — Why Not STOP Then START10.3Transaction Atomicity and Bus Ownership Across Phases
Module 11
Key I²C Timing Parameters
11.1Why I²C Timing Parameters Exist11.2f(SCL), tLOW and tHIGH — The Clock Envelope11.3tSU;DAT and tHD;DAT — The Data Window11.4tVD;DAT and tVD;ACK — Data Valid Time11.5tSU;STA and tHD;STA — START and Repeated-START Margins11.6tSU;STO and tBUF — STOP and Bus-Free Time11.7tr, tf and Cb — The Electrical Envelope11.8tSP — Spike Suppression and the Input Filter11.9Building an I²C Timing Budget
Module 12
Clock Stretching
12.1Why Clock Stretching Exists12.2The Stretching Mechanism — Holding SCL Low12.3Where a Target May Stretch, and What It Costs12.4Stretch Bounds, Timeouts and the No-Assumption Rule
Module 13
Multi-Master, Arbitration & Clock Synchronization
13.1Why Multiple Masters Exist13.2SCL Synchronization — How Masters Agree on One Clock13.3SDA Arbitration — Wired-AND Decides Bit by Bit13.4Losing Arbitration — Detection, Correct Behavior and Bus Ownership13.5Arbitration Worked Examples and Corner Cases
Module 14
Speed Modes & Timing Limits
14.1Standard, Fast and Fast-Mode Plus — The Mainstream Modes14.2High-Speed Mode — Master Code, Current Source and Bridging14.3Ultra-Fast Mode — The Push-Pull, Write-Only Outlier14.4Choosing a Speed Mode — Pull-Ups, Capacitance and Design Cost
Module 15
Special & Reserved Protocol Features
15.1General Call and Broadcast Addressing15.2Software Reset and Device ID15.3SMBus and PMBus — Stricter Profiles Built on I²C15.4Bus Clear and Recovery — The Protocol-Level Escape Hatch
Module 16
Register-Based Devices, EEPROMs & Sensors
16.1The Register-Map Model — From Datasheet to Transactions16.2EEPROM Access — Word Address, Random Read and Sequential Read16.3Page Writes and Write-Cycle Boundaries16.4Acknowledge Polling and Device-Busy Behavior16.5Real Device Access Patterns — Sensors, RTCs and PMICs
Module 17
I²C Master RTL Design
17.1From Requirements to Architecture — Decomposing an I²C Master17.2The Host Command Interface — Register Model and On-Chip Bus Wrapping17.3The SCL Timing Generator17.4SDA Open-Drain Control and Line Ownership in RTL17.5START and STOP Generation17.6The Bit Engine — Driving and Sampling One Bit17.7The Byte Engine — Eight Bits and the ACK Slot17.8Transaction Control — Write, Read and Master ACK Policy17.9Repeated START and Combined-Transaction Control17.10Bus Feedback — Clock-Stretch Detection and Arbitration Loss17.11Timeout, Error Handling and Bus Recovery17.12Deriving the Master FSM from the Architecture17.13Parameterization, Reset and Synthesis Considerations
Module 18
I²C Slave RTL Design
18.1Slave Requirements — Responding Without Owning the Clock18.2Sampling SDA and SCL — Edge Detection Inside a Slave18.3START and STOP Detection18.4Address Shift Register, Address Match and Direction Decode18.5ACK Generation and Its Timing Window18.6The Receive Datapath — Capturing Written Bytes18.7The Transmit Datapath — Sourcing Read Data in Time18.8Detecting the Master's ACK or NACK on a Read18.9The Register Interface Behind the Slave18.10Repeated START, Transaction State and Clock Stretching18.11Deriving the Slave FSM, Reset Behavior and Error Recovery
Module 19
FPGA & Implementation Engineering
19.1Modeling Open Drain — 0/Z, Output Enable and What Synthesis Infers19.2Tri-State Buffers and FPGA I/O Primitives19.3External Pull-Ups vs Internal Weak Pull-Ups19.4Asynchronous SDA/SCL Inputs — Metastability and Synchronization19.5Oversampling, Edge Detection and Spike Filtering19.6Clock Domains and Timing Constraints for an I²C Block19.7Simulation vs Synthesized Hardware — Where Behavior Diverges19.8Hardware Bring-Up and On-Chip Debug19.9FPGA as Master and as Target — Integration Patterns
Module 20
I²C Verification Architecture
20.1Verification Objectives and the I²C Test Plan20.2The Protocol Feature Matrix — Deciding What Must Be Covered20.3What Should an I²C Transaction Object Represent?20.4Active and Passive Components — Agents, Monitors and Responders20.5The Master Agent — Stimulus That Owns the Bus20.6The Target Responder — Modeling a Real Device20.7Monitor Architecture and Transaction Reconstruction20.8Reference Model and Scoreboard Strategy20.9Protocol Checking and Error-Injection Strategy
Module 21
SystemVerilog / UVM Verification
21.1The i2c_if Interface — Bidirectional Signals in a Testbench21.2The Sequence Item — Fields, Constraints and Direction21.3The Master Driver — Driving an Open-Drain Bus from a Testbench21.4The Target Responder Driver — Reacting Within Protocol Timing21.5The Monitor — Sampling the Bus Without Disturbing It21.6Transaction Reconstruction in the Monitor21.7Assembling the I²C Agent21.8The Environment — Agents, Scoreboard, Coverage and Configuration21.9Sequencer and Sequences — Write, Read and Combined Transactions21.10Negative and Error Sequences21.11Building a Reusable I²C VIP
Module 22
Assertions, Coverage & Corner Cases
22.1Assertion or Scoreboard? Deciding Where a Rule Lives22.2Asserting the Data-Valid Rule — SDA Stable While SCL Is High22.3Asserting Legal START, Repeated START and STOP22.4Asserting ACK Timing and Byte Boundaries22.5Asserting Clock-Stretching, Arbitration and Bus-Idle Behavior22.6A Functional Coverage Model for I²C, and the Crosses Worth Writing22.7Negative Testing — NACK, Truncated Bytes and Malformed Framing22.8Corner Cases — Stuck Lines, Excessive Stretch and Reset Mid-Transaction22.9Verifying Stretching and Arbitration Without Flaky Tests
Module 23
I²C Debugging & Failure Analysis
23.1A Systematic I²C Debug Workflow23.2Reading a Capture — Framing, Address, ACK and the First Bad Byte23.3Protocol Bug or Electrical Bug? Splitting the Search Space23.4Missing ACK and Address Faults23.5Missing Pull-Ups, Slow Rise Times and Noise23.6Stuck Bus — Diagnosis and Recovery23.7Clock-Stretching and Arbitration Failures in the Field23.8RTL and FPGA Bugs That Only Appear on Hardware
Module 24
Engineering Review, Judgment & Synthesis
24.1RTL Design Review — Master and Slave24.2Verification Completeness Review24.3Electrical, Timing and Bring-Up Readiness Review24.4I²C Misconceptions Engineers Still Get Wrong24.5Reasoning About Open-Drain, Pull-Ups and Rise Time24.6Reasoning About Clock Stretching24.7Reasoning About Multi-Master Arbitration24.8Designing an I²C Master at the Whiteboard