Electrical Fundamentals

Every waveform in this module has carried the same warning: this is a logical view; it depicts no voltages, no rise times and no margin. Every RTL block has declared that its inputs are already-thresholded digital values. Chapter 3.2 separated deterministic logic failures from statistical physical ones and then stopped at the boundary.

This chapter goes below it — and it is the chapter that has to be most careful about its own limits. An honest treatment of the electrical layer includes saying clearly which questions a digital engineer can answer, which require instruments, and which belong to specialists whose work this curriculum can describe but not replace. A tutorial that implied otherwise would be teaching false confidence, which on this layer is expensive.

1. Why Transitions Are Bounded at Both Ends

Start with a specification that surprises people: USB constrains how fast a signal may transition, not merely how slow.

The minimum is obvious. A transition that takes too long relative to the bit period does not complete before the next one is due, so the signal never reaches a definite level and the receiver's decision degrades. That is the familiar constraint and it is why faster signalling demands faster edges.

The maximum is the interesting one. A transition faster than necessary is not free, and it costs in three ways.

It radiates more. The energy a signal couples into its surroundings rises with how sharply it changes. A needlessly fast edge is a needlessly effective transmitter of interference into everything nearby — including, as Chapter 3.2 §4 noted, conductors that may not receive it equally, turning it into differential noise somewhere else.

It reflects more. The faster the edge, the shorter the physical distance over which its energy is distributed, which makes the transmission line's imperfections matter more. Discontinuities that are invisible to a slow edge become significant to a fast one, and §2 is about why that matters.

It couples more into its own neighbour. Faster edges crosstalk harder, including from one conductor of a pair into the other.

So the specification defines a window: fast enough to resolve within the bit period, slow enough not to create problems that did not need to exist. An edge-rate specification with only a minimum would be an incomplete specification, and recognising that is the first piece of electrical literacy this chapter offers — it generalises to essentially every high-rate interface you will meet.

This is also where low speed and full speed genuinely differ beyond their rates. A slower signalling rate permits — and requires — slower edges, which is one reason low speed is more tolerant of cabling that full speed would not accept.

2. Controlled Impedance, and What a Cable Is

A cable is not a pair of wires. Electrically it is a transmission line, and at the transition speeds involved that distinction is not pedantry.

A transmission line has a characteristic impedance — a property of its geometry and materials rather than its length. For USB's differential pair the nominal figure is 90 Ω differential, and a cable is built to hold it.

Why it matters is reflection. When a signal travelling along a line meets a point where the impedance changes, part of its energy reflects back toward the source rather than continuing. The reflected energy returns, possibly reflects again, and arrives at the receiver at the wrong time — superimposed on whatever legitimate signal is there.

Three consequences follow that a digital engineer should hold.

Reflections are differential-mode and therefore not rejectable. Chapter 3.2's common-mode rejection does nothing about them: the reflection is part of the signal on the pair, inside the quantity the receiver measures. This is why impedance control is a separate discipline from noise rejection rather than an aspect of it.

Discontinuities are where impedance changes — connectors, vias, stubs, a change of medium, a damaged section of cable, a badly matched driver or receiver. Every joint in the path is a candidate.

And the effect scales with edge rate, which closes the loop with §1: this is precisely why edges are bounded above. A slower edge is less sensitive to a given discontinuity, so the two specifications are solving one problem together.

Termination is the countermeasure: arranging the impedance seen at the ends of the line so that arriving energy is absorbed rather than reflected. High-speed USB operation terminates each conductor to ground at nominally 45 Ω, which presents the 90 Ω differential impedance the cable is built for — the numbers are related by design rather than by coincidence.

3. Why High Speed Abandons the Pull-Up

Chapter 3.7 said that a device switching to high-speed operation removes its pull-up, and deferred the reason. It is a termination argument, and it is the cleanest illustration in this module of why the electrical layer constrains the architecture above it.

High-speed operation requires the terminations of §2. Those terminations are resistances to ground on both conductors — deliberately low, because their job is to match the line.

A 1.5 kΩ pull-up to a supply cannot coexist usefully with that. Against a 45 Ω termination it is electrically negligible, so it no longer performs the announcement of Chapter 3.5; and to whatever extent it does anything, it is an unwanted DC offset on a line whose whole design is now about presenting a matched impedance. The mechanism that made low and full speed work is actively unhelpful in the electrical arrangement high speed requires.

Hence the sequence: attach claiming full speed, using the pull-up because it is the only thing that works with nothing agreed; negotiate; and if the negotiation succeeds, change the electrical arrangement entirely — terminations in, pull-up out. The device is not being coy. It is moving between two genuinely different electrical worlds, and it uses the first one's mechanism to arrange the transition into the second.

Note the other differences the figure records. High-speed signalling uses a substantially smaller differential swing than full speed. A smaller swing costs less energy and radiates less, and it is affordable only because the line is terminated and controlled — you can work with a small signal when you have removed the things that would corrupt it. That is a trade, and it is why high-speed operation is far less tolerant of poor cabling than full speed: it spent its margin on speed and efficiency and relies on the physical layer to have been done properly.

4. What Each Instrument Can See

This is the practically useful part of the chapter, and it is the counterpart of the monitoring model Chapter 3.1 §7 introduced.

A logic analyser observes digital signals, often after a PHY has already made its decisions. It shows you what the digital domain concluded. It cannot show you how close that conclusion was to being different, because by the time it observes, the margin question has been answered and discarded.

An oscilloscope, differentially probed, observes the actual signal on the conductors. It shows levels, edge rates, overshoot, reflections and how much room the receiver had. It is the only instrument in this list that can answer was there margin?

A protocol analyser observes at the packet level and above. It shows what was communicated and what failed, which is excellent for finding that something went wrong and structurally unable to say why at the electrical layer.

A bit-error-rate measurement observes statistics over time. It quantifies how often the link fails, which is exactly the quantity §5 says matters for the failures that live at this layer.

The useful principle is that no instrument sees another's abstraction. A protocol analyser reporting errors tells you the link is failing; it cannot distinguish a marginal signal from a logic bug. A logic analyser showing correct digital values tells you the decisions were right; it cannot tell you they were nearly wrong. An engineer who reaches for one instrument and concludes from its silence is making a claim the instrument never supported — which is Chapter 3.2 §5's point about digital regressions, generalised to the bench.

5. What a Digital Engineer Can and Cannot Conclude

Being explicit about this is the most valuable thing this chapter can do for an RTL or DV engineer.

You can conclude, from digital evidence:

That decode logic is correct or incorrect, since that is deterministic and reproducible. That a failure is deterministic — it recurs identically on identical stimulus — and therefore is in the digital domain. That state machines, counters, qualification and clock-domain crossings behave as specified. And that a failure correlates with a logical variable such as speed, device type or traffic pattern, which points at logic.

You cannot conclude, from digital evidence:

That the electrical layer is healthy. A passing simulation contains no cable, no margin, no reflection and no interference, so its silence is a property of the model. That a marginal signal is fine because it was decoded correctly today — margin is precisely what a correct decode does not tell you about. That an intermittent failure is not electrical, since intermittency is the electrical layer's characteristic signature rather than evidence against it.

And the discriminating question remains the cheapest one available: is the failure deterministic or statistical? Deterministic, reproducible, correlated with logical variables points inside the digital domain. Statistical, rate- or cable- or temperature-dependent, varying between nominally identical units points below it — and there, more digital tests will all pass while measuring nothing.

6. Common Misconceptions

7. Reason It Through

A product passes all testing with the supplied cable. A customer using a long third-party cable reports that high-speed devices fail while full-speed devices on the same cable work perfectly. The failure rate rises with the cable's length.

What does the speed selectivity tell you? A great deal, because it is the chapter's central asymmetry made visible. Full speed uses a larger swing, slower edges and no dependence on termination; high speed uses a small swing on a line whose correctness depends on controlled impedance. A cable that degrades the signal or presents the wrong impedance can therefore remain comfortably adequate for one and inadequate for the other. The two speeds are not the same test.

What does the length correlation tell you? That the cause accumulates with the physical path — attenuation, or discontinuities whose count grows with length, or a characteristic impedance that is simply wrong and whose effect compounds.

Is this a logic problem? Almost certainly not, and the evidence is structural rather than circumstantial. It is statistical, correlates with a physical variable, differs between cables, and involves no change to any digital behaviour. §5's discriminating question answers itself.

Why is “full speed works” not reassurance? Because it confirms the diagnosis rather than weakening it. Full speed working proves the conductors are connected and the device functions; that high speed does not proves the failure is in the quantities high speed depends on and full speed does not — which is exactly the margin the cable was supposed to provide.

What would you actually measure, and what would you not? Measure the signal differentially at the receiver with an oscilloscope, and examine the cable's impedance. Do not add digital tests: they will pass, because nothing in the digital domain is wrong.

The general lesson. A failure that appears at one speed and not another, on the same hardware, is evidence about margin — because the speeds differ in exactly how much margin they require. That is among the most informative experiments available on a physical interface, and it costs one cable swap.

8. Understanding Check

9. Summary

Edge rate is bounded at both ends. Too slow and the signal cannot resolve within the bit period; too fast and it radiates, reflects and crosstalks more than it needed to. A specification with only a minimum would be incomplete — a point that generalises to essentially every high-rate interface.

A cable is a transmission line with a characteristic impedance, nominally 90 Ω differential. Where impedance changes, energy reflects and returns to the receiver at the wrong time. Reflections are differential-mode and therefore not rejectable — impedance control and termination are a separate discipline from noise rejection, not an aspect of it. Their effect scales with edge rate, which is why the two specifications solve one problem together.

High speed is a different electrical arrangement, not faster full speed: terminations of nominally 45 Ω per conductor presenting the cable's 90 Ω differential, a much smaller swing, and no pull-up — which is why a device removes it, since it is negligible against the termination and unhelpful on a line that must present a matched impedance. The small swing is affordable only because the line is controlled, which is why high speed is far less tolerant of poor cabling.

No instrument sees another's abstraction. A logic analyser shows conclusions, an oscilloscope shows margin, a protocol analyser shows outcomes, a bit-error-rate measurement shows statistics. Concluding health from one instrument's silence claims something it never supported.

And the boundary an engineer must keep: digital evidence establishes logic correctness and identifies deterministic faults; it establishes nothing about the electrical layer, because the model contains none of the relevant quantities. Deterministic or statistical remains the cheapest discriminating question available.

10. What Comes Next

Module 3 is complete. The physical layer now has a full account: four named line states and the receiver structure that produces them; a differential measurement and the conditions its benefit depends on; two conductors with asymmetric roles; a J that is not a voltage but a name whose polarity follows the speed; a resistor that announces presence and speed by winning a contest; pull-downs that make absence itself a recognisable condition; a negotiation that adds a third speed the static mechanism could not express; and the electrical quantities underneath all of it, with an explicit account of what a digital engineer may and may not conclude.

What Module 3 has deliberately not touched is meaning. Every line state in this module was a condition, not a message — and how a sequence of them becomes bits, and those bits a packet, is a question later modules answer.

Module 4 asks something else first: why there had to be more than one USB at all. This module described a physical layer; Chapter 4.1 begins by observing that it is the physical layer of the first generation, and that everything about it was rebuilt more than once while the device model above it was never touched. That is the story of USB's generations, and it is where the curriculum goes next.

Module 3's contribution to everything that follows is the vocabulary: everything above the physical layer is built out of transitions between the states this module defined — and, just as importantly, you now know which of those states mean different things at different speeds.

Browse the full path on the USB tutorials index.