USB — Tutorials · VLSI Mentor

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31Modules

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Architecture first, packets later

Host-centric model, tiered-star topology, and the enumeration sequence before bit-level packets — the mental model that turns USB from a spec into an engineering discipline.

Interview-ready depth

A dedicated interview module plus per-chapter interview weighting — enumeration, endpoints, transfer-type selection, scheduling, xHCI architecture, silicon-bring-up debug.

Design → verify → debug

Device-controller RTL (endpoints, FIFOs, protocol FSMs), SVA / UVM verification with VIPs, and protocol-analyser-driven debugging — the full engineering loop.

USB Complete Curriculum

Your Learning Roadmap

180 chapters · 31 modules — host-centric architecture, enumeration, endpoints, and xHCI scheduling.

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Module 1

Why USB Exists

1.1The Peripheral-Connectivity Problem 1.2Legacy Peripheral Interfaces 1.3RS-232 Recap 1.4The Parallel Port 1.5PS/2 Keyboard / Mouse 1.6Why USB Was Created 1.7The Universal-Connectivity Vision 1.8USB Evolution Timeline

Module 2

USB Architecture Overview

2.1The USB Host 2.2The USB Device 2.3USB Hubs 2.4The Root Hub 2.5The Host Controller 2.6The Host-Centric Model 2.7USB Topology 2.8Tiered-Star Architecture

Module 3

USB Physical Layer

3.1USB Signalling Overview 3.2Differential Signalling 3.3The D+ Line 3.4The D- Line 3.5Pull-Up Resistors 3.6Pull-Down Resistors 3.7Speed Detection 3.8Electrical Fundamentals

Module 4

USB Generations

4.1USB 1.x Architecture 4.2USB 2.0 Architecture 4.3USB 3.x Architecture 4.4USB4 Architecture 4.5Architectural Evolution 4.6Speed Improvements 4.7USB Backward Compatibility

Module 5

USB Speed Modes

5.1Low Speed (LS)5.2Full Speed (FS)5.3High Speed (HS)5.4SuperSpeed (SS)5.5SuperSpeed+ and Beyond

Module 6

USB Enumeration

6.1Device Connection 6.2USB Reset 6.3Address Assignment 6.4Descriptor Discovery 6.5Configuration Selection 6.6End-to-End Enumeration Flow 6.7Enumeration Timing

Module 7

USB Descriptors

7.1Device Descriptor 7.2Configuration Descriptor 7.3Interface Descriptor 7.4Endpoint Descriptor 7.5String Descriptor 7.6BOS Descriptor

Module 8

USB Device States

8.1Attached State 8.2Powered State 8.3Default State 8.4Addressed State 8.5Configured State 8.6Suspended State

Module 9

USB Endpoints

9.1The Endpoint Concept 9.2Endpoint Addressing 9.3Endpoint Numbers 9.4Endpoint Direction 9.5Endpoint Buffers

Module 10

USB Transfer Types

10.1Four Transfer Types Overview 10.2Control Transfers 10.3Bulk Transfers 10.4Interrupt Transfers 10.5Isochronous Transfers

Module 11

USB Packets

11.1Token Packets 11.2Data Packets 11.3Handshake Packets 11.4SOF Packets 11.5USB Packet Structure 11.6CRC in USB

Module 12

USB Transaction Model

12.1Token Stage 12.2Data Stage 12.3Handshake Stage 12.4Transaction Flow 12.5Transaction Timing Relationships

Module 13

Control Transfers

13.1Setup Stage 13.2Control Data Stage 13.3Status Stage 13.4Standard Device Requests 13.5Enumeration as Worked Example

Module 14

Bulk Transfers

14.1Bulk Throughput 14.2Bulk Reliability 14.3Bulk Retries 14.4Bulk for Storage Devices 14.5Bulk for Data Streaming

Module 15

Interrupt Transfers

15.1The Polling Model 15.2Keyboards on USB 15.3Mice on USB 15.4Interrupt Latency Requirements

Module 16

Isochronous Transfers

16.1Audio over Isochronous 16.2Video over Isochronous 16.3Real-Time Data Streams 16.4Bandwidth Reservation 16.5Isochronous Error-Handling Tradeoffs

Module 17

USB Scheduling

17.1Frame Scheduling (1 ms)17.2Microframe Scheduling (125 µs)17.3Host Scheduling Algorithm 17.4Bandwidth Allocation 17.5Transaction Timing on the Bus

Module 18

USB Hubs

18.1Hub Architecture 18.2Port Management 18.3Downstream Device Discovery 18.4Cascading Hubs 18.5Hub Power Management

Module 19

USB Power Management

19.1Bus Power 19.2Self Power 19.3Suspend 19.4Resume 19.5Remote Wakeup 19.6Power Budgeting

Module 20

USB 3.x Architecture

20.1SuperSpeed Concepts 20.2Dual-Bus Architecture 20.3Link Training 20.4USB 3.x Packets 20.5USB 3.x vs USB 2.0 Differences

Module 21

USB Device Controller Design

21.1Endpoint Logic 21.2FIFO Architecture 21.3Descriptor Engine 21.4Protocol Engine 21.5Controller FSMs

Module 22

USB Host Controller Overview

22.1EHCI Overview 22.2xHCI Overview 22.3Host-Side Scheduling 22.4Host Resource Management

Module 23

USB RTL Design

23.1Device Controller RTL 23.2Endpoint RTL 23.3FIFO Design 23.4Protocol FSMs 23.5Timing Considerations

Module 24

USB Verification

24.1USB Protocol Checkers 24.2USB Assertions 24.3USB Scoreboards 24.4USB Functional Coverage 24.5USB VIP Usage 24.6UVM Architecture for USB

Module 25

USB Debugging

25.1Enumeration Failures 25.2Descriptor Issues 25.3Endpoint Problems 25.4Transfer Errors 25.5CRC Errors 25.6Power Issues 25.7Using a Protocol Analyser

Module 26

USB in SoCs

26.1USB Controllers on SoC 26.2DMA Integration 26.3AXI Interfaces to USB 26.4USB Interrupt Integration 26.5Firmware Interaction

Module 27

USB Interview Mastery

27.1What Is USB?27.2Host / Device / Hub Identification 27.3Enumeration Question 27.4Endpoints Question 27.5Transfer-Types Question 27.6Scheduling Question 27.7Senior Host-Controller Architecture 27.8Senior Verification Strategy 27.9Senior Silicon Debug 27.10Senior Architecture Tradeoffs

Module 28

USB vs Other Protocols

28.1USB vs UART 28.2USB vs SPI 28.3USB vs Ethernet 28.4USB vs PCIe

Module 29

Real Industry Case Studies

29.1USB Flash Drives 29.2USB Webcams 29.3USB Audio Devices 29.4Smartphones over USB 29.5USB in Embedded Devices 29.6USB on FPGA Development Boards

Module 30

USB Design-Review Checklist

30.1RTL Review Checklist 30.2Verification Review Checklist 30.3Compliance Review Checklist 30.4Integration Review Checklist 30.5Debug Review Checklist 30.6Interview Review Checklist

Module 31

USB Misconceptions Engineers Have

31.1“USB Is Point-to-Point Only”31.2“USB Devices Initiate Transfers”31.3“Endpoints Are Physical Ports”31.4“Bulk Transfers Are Always Fastest”31.5“Enumeration Is Optional”31.6“USB 3.x Is Just Faster USB 2.0”