Shared MOSI, Shared MISO, Individual CS

Chapter 8.1 established what selecting a device means. This chapter is about the wiring that makes selection work for several devices at once — and about the constraint that decides how many "several" can be.

Three of SPI's four signals are shared and one is not. Which is which, why, and what does that cost as the device count grows?

The answer is the reason SPI is the obvious choice for three peripherals and an awkward one for thirty.

1. What "Shared" Means for Each Signal

The four signals are shared in three genuinely different senses, and conflating them is the source of most multi-slave confusion.

SCLK — one driver, many listeners, always. The master drives it; every device receives it continuously whether selected or not. There is no contention risk because there is only ever one driver, and a deselected device simply ignores the edges (Chapter 8.1 §1).

MOSI — one driver, many listeners, always. Identical in structure to SCLK. Every device sees every bit the master sends, including bits intended for others, and deselected devices must shift nothing.

MISO — one driver at a time, and that is the whole problem. Every device has an output on this net, and the net works only because exactly one of them is enabled at any instant (Chapter 8.3). This is the only signal where being shared creates a real hazard.

CS — not shared at all. One dedicated line per device, which is what makes the other three safe.

2. The Standard Wiring

Two properties of this arrangement are worth stating because the alternatives in §4 give one or both of them up.

Every device is independent. Adding one does not change any other's timing, protocol or configuration. Devices with different modes, widths and speeds coexist, because each transaction is entirely between the master and one device.

Every transaction is a direct exchange. No device sees another's data, no ordering is imposed, and a failure in one device cannot corrupt another's transfer — provided the MISO discipline holds.

3. The Pin Arithmetic

For N devices the independent topology costs:

   pins = 3 shared (SCLK, MOSI, MISO) + N select lines

Which is fine until it is not:

    N       pins      comment
    1         4       the minimum
    2         5
    4         7       comfortable on any microcontroller
    8        11       starting to matter
   16        19       usually forces a decoder
   32        35       impractical on most parts

The growth is linear and the base is tiny, so SPI is extremely economical at small N and steadily worse at large N. Compare I²C, which is two pins regardless of device count — the addressing that costs SPI nothing on the wire costs it a pin per device instead.

That trade is the honest summary of when to choose which: SPI buys speed and simplicity with pins; I²C buys pins with bus time and complexity. Neither is better, and a system with three fast devices and twelve slow ones often uses both.

4. Four Ways to Spend Fewer Pins

Decoded selects. Drive an index through an external decoder, as Chapter 8.1 §11 worked through. Cost: 3 + ceil(log2(N)) + 1 pins, where the extra one is the decoder's enable — without it there is no all-deselected state.

   N = 8    →  3 + 3 + 1  =  7 pins   (against 11)
   N = 16   →  3 + 4 + 1  =  8 pins   (against 19)
   N = 32   →  3 + 5 + 1  =  9 pins   (against 35)

The saving grows dramatically with N. The costs are an external part, a gate delay on the select path, and the loss of any ability to assert two selects deliberately.

Daisy chain. Wire the devices' shift registers in series — one device's MISO into the next one's MOSI — so the whole chain is one long shift register with a single shared select. Cost: 3 + 1 pins, regardless of N.

That is the cheapest possible arrangement and it changes the protocol fundamentally: every transaction addresses all devices, the data for device k must be positioned correctly in a chain-length-sized transfer, and the devices must support the mode. It is common on LED drivers and shift-register expanders and rare elsewhere, because most devices are not built for it.

Multiple buses. Use k independent SPI controllers. Cost: 3k + N pins — worse, not better. The reason to do it is not pins but concurrency and speed: two buses can transfer simultaneously, and each can run at the speed of its slowest device rather than the system's slowest.

Bus switches or muxes. An analogue switch isolating groups of devices. Cost: pins for the switch control, plus propagation delay and signal-integrity degradation on every line it passes. Occasionally the right answer when two devices genuinely cannot share a net — for example, a long cable to an off-board device.

The comparison as a table:

5. Why This Chapter Has No RTL

Deliberate, and the reason is the subject.

This chapter is about wiring and pin budgets — board-level facts. The hardware that makes the topology work already exists: Chapter 8.1 built the select generator that drives the select lines, and Chapter 8.3 builds the output-enable controller that makes a shared MISO net safe. There is no third module between them; the topology is what you get by connecting those two across several devices.

Writing RTL here would mean inventing a "topology module", which is not a thing any design contains. The honest artifacts for a chapter about wiring are the diagram, the arithmetic of §3, and the comparison of §4 — all of which are what an engineer actually uses when choosing one.

6. Why a Verification Engineer Cares

The topology decides what a testbench must model, and getting that wrong produces an environment that cannot see the interesting failures.

A single-slave testbench cannot find a contention bug. With one device on the model's MISO, the output enable is never in competition and the bug class of Chapter 8.5 is structurally absent. The environment must instantiate at least two slave models sharing a net.

The shared net must be modelled as a shared net. Connecting each slave model's MISO to a separate signal and multiplexing by selection is the obvious shortcut and it defeats the purpose: the multiplexer resolves what the real bus cannot, so two simultaneous drivers produce a clean value instead of a conflict:

   // A wired net in SystemVerilog. Two active drivers yield X, which is what
   // makes contention VISIBLE in simulation. Multiplexing by chip select
   // would hide exactly the failure the model exists to expose.
   wire miso;
   assign miso = slave0_oe ? slave0_do : 1'bz;
   assign miso = slave1_oe ? slave1_do : 1'bz;
   assign miso = slave2_oe ? slave2_do : 1'bz;

   // The pull-up that a real board has. Without it, "nobody driving" is z
   // rather than a defined level, and a test cannot distinguish an undriven
   // net from a driven-low one -- the same ambiguity as on real hardware
   // (Chapter 6.5 §2).
   pullup (miso);

   // Contention is then an X on the net, which the checker watches for.
   always @(posedge clk)
       if (cs_active && miso === 1'bx)
           `uvm_error("CONTENTION", "two slaves driving MISO simultaneously")

Coverage must include the device count and the switching pattern:

   covergroup spi_topology_cg @(posedge cs_rose);
       cp_n_slaves : coverpoint env_cfg.n_slaves {
           bins one    = {1};       // cannot exercise sharing at all
           bins two    = {2};       // the minimum that can contend
           bins many   = {[3:16]};
       }

       // Which device followed which. A suite that always talks to the same
       // device, or always cycles in order, misses the handovers that matter.
       cp_handover : coverpoint {prev_slave, curr_slave} iff (n_slaves > 1) {
           bins same      = {[0:$]} with (item[7:4] == item[3:0]);
           bins different = default;
       }

       cp_mixed_mode : coverpoint slaves_have_different_modes {
           bins uniform = {0};
           bins mixed   = {1};      // a real bus, and a common source of bugs
       }
   endgroup

cp_mixed_mode is worth insisting on. The independent topology's selling point is that devices need not agree on mode, width or speed — and a testbench in which every slave model is configured identically has never tested that claim, while a real board almost always mixes them.

7. Why an FPGA or ASIC Engineer Cares

MISO is a shared net and needs a pull-up. When no device is selected, nothing drives it and it floats. A floating input on the master oscillates, draws current in the input buffer, and makes "no device responding" indistinguishable from "device returning zeros" (Chapter 6.5 §2). A resistor of a few tens of kilohms fixes all three.

Fan-out on SCLK is a real load. Every device presents input capacitance, and eight devices on one clock net is eight times the load plus the trace. That slows edges, and slow edges at high frequency are the signal-integrity problem of Chapter 1.6. Above a handful of devices, a clock buffer or a deliberate topology — a star rather than a daisy-chained stub — starts to matter more than the protocol does.

Select lines are the cheapest thing to get wrong on a schematic. They are individually routed, individually named, and nothing on the bus verifies that CS3 goes to the device the firmware calls device 3. A swapped pair produces §8's failure, and the only defence is a deliberate check during bring-up.

Pin cost is a system-architecture decision, not an afterthought. If the pin budget is tight, the choice between a decoder, a second bus and moving slow devices to I²C should be made early — all three have board consequences that are expensive to revisit.

8. Failure Signature — Adding a Fourth Device Breaks the Other Three

Symptom. A working three-device SPI bus has a fourth device added. The new device works. The three existing devices now return corrupted data intermittently, and the corruption correlates with how recently the new device was accessed.

What "the new device works" establishes. Its wiring, mode and select are all correct. The fault is in its effect on the bus, not in the device itself — which immediately points at the one signal where devices interact: MISO.

Plausible mechanisms.

• The new device does not release MISO when deselected — either it lacks a proper tri-state, its select is mis-wired, or it is an active-high part driven active-low (Chapter 8.1 §9). Its driver then fights every other device's.
• Its release is too slow, so it overlaps the next device's assertion (Chapter 8.4).
• The added capacitive load has slowed SCLK edges past what the existing devices tolerate — a genuinely different mechanism with the same trigger.
• The fourth select line was taken from a pin that was already doing something else.

The discriminating observation. Remove the new device from the software rotation but leave it fitted, and see whether the corruption stops. If it does, the fault is its behaviour when accessed, so suspect the release or the turnaround. If corruption continues with the part fitted but never selected, the fault is static — a permanently-enabled driver or a mis-wired select — and the part is fighting the bus continuously rather than during handover.

That single experiment separates a dynamic turnaround problem from a static wiring one, and it needs no instrument.

Why the investigation goes wrong. Because the new device works, so it is presumed innocent and the search goes to the three that broke. They did not change. On a shared medium the newest driver is always the first suspect, and "it works" says only that it can talk — not that it knows when to stop.

9. Common Misconceptions

10. Reason It Through

Work this before reading the answer.

A design has a 48-pin microcontroller with 11 free GPIOs. It must talk to: a 50 MHz flash, a 20 MHz display controller, four 1 MHz temperature sensors, and two 100 kHz EEPROMs — eight devices in total.

The obvious approach needs 3 + 8 = 11 pins, which exactly fits. Is that the right design?

It fits, and it is a poor design. Three separate problems, none of which is about pin count.

Every pin is consumed. Using all eleven free GPIOs leaves nothing for a reset line, an interrupt from a sensor, a status LED or a debug pin. A design with zero margin on its scarcest resource will need a respin the first time a requirement is added.

Every device is forced to the same bus speed. All eight share SCLK, so a transaction to the flash and a transaction to an EEPROM run at whatever rate the controller is currently configured for. Reconfiguring the divider between transactions is possible and costs time on every switch (Chapter 2.1); not reconfiguring means running the flash at 100 kHz, which wastes a factor of 500.

The slow devices dominate the electrical environment. Eight devices of capacitive load on SCLK and MOSI, to serve one part that wants 50 MHz — the edges are slowed by devices that do not need speed at all.

The better architecture splits by speed rather than by pin count.

Put the flash on its own bus. It is the only device that justifies 50 MHz, and alone on a net it sees minimal load. Cost: 4 pins.

Move the six slow devices to I²C. The four sensors and two EEPROMs are all slow, and almost all such parts exist in I²C variants. Cost: 2 pins for all six, and they get addressing instead of select lines.

Leave the display on the remaining SPI bus. Cost: 4 pins.

   SPI bus A (flash)          4 pins
   SPI bus B (display)        4 pins
   I²C (6 slow devices)       2 pins
   ─────────────────────────────────
   total                     10 pins,  one to spare

That is fewer pins and better: the flash runs at full speed, the slow devices cannot slow anything down, and there is margin.

The general lesson. "It fits" is not a design justification. Pin count is one constraint among several, and on a mixed-speed system it is usually not the binding one — bus speed and electrical loading are. The right question is not how do I connect eight devices but which of these devices actually belong on the same bus, and the answer is usually grouped by speed.

11. Understanding Check

12. Summary

SPI's signals are shared in three different senses. SCLK and MOSI are fan-out — one driver, many listeners, no coordination and no hazard. MISO is a shared medium where every device has an output and exactly one may be enabled. CS is not shared, and that is what makes the rest safe.

Every contention failure in this module lives on MISO, and none on the fan-out signals.

The independent topology costs 3 + N pins, which is four for one device and thirty-five for thirty-two. Linear growth from a tiny base makes SPI excellent for a few devices and awkward for many — the mirror of I²C, which costs two pins regardless and pays in bus time instead.

The alternatives trade differently. Decoded selects cost 3 + ⌈log₂N⌉ + 1, where the enable is not optional because it restores the all-deselected state. Daisy chaining costs 3 + 1 and changes the protocol fundamentally. Multiple buses cost more pins and are chosen for concurrency and per-bus speed, not economy.

For verification the topology decides what must be modelled: at least two slaves on a genuinely wired net, so that two drivers resolve to X rather than being cleanly multiplexed — and with different modes, since device independence is the topology's selling point and a uniformly-configured testbench has never tested it.

On the board, MISO needs a pull-up, SCLK's fan-out load becomes the limiting factor before the protocol does, and select lines are individually routed with nothing on the bus to verify that each reaches the device the firmware believes.

13. What Comes Next

The shared MISO net works only because exactly one device drives it at a time. Chapter 8.3 — Slave Output Enable and MISO Tri-State builds the mechanism that enforces that: when a slave may take the line, when it must let go, why letting go must be faster than taking hold, and the output-enable controller that makes the dead gap between two drivers structural rather than accidental — in all three HDLs.