Reserved Addresses and the I²C Address Map

   total seven-bit addresses                      2^7  =  128

   reserved group 1:  0000XXX  =  0x00 .. 0x07           8
   reserved group 2:  1111XXX  =  0x78 .. 0x7F           8
                                              reserved  16

   allocatable                              128 - 16  =  112

   The 112 is the number worth remembering, and it is smaller than it looks:
   every part from every vendor draws from the same 112, and a great many of
   them ship with a fixed address chosen from a narrow customary range.

   // Purely combinational decode of the reserved-address map. Encodes UM10204
   // Table 3 and the two footnotes that FORBID a device from responding.
   module i2c_address_classifier (
       input  logic [6:0] addr,          // the seven address bits
       input  logic       rw,            // the eighth bit on the wire
       output logic       is_reserved,   // the ADDRESS lies in a reserved group
       output logic [3:0] addr_class,    // the specific purpose, see localparams
       output logic       must_not_ack   // the specification forbids responding
   );
       // Class codes. CLS_USABLE is everything the map does not claim.
       localparam logic [3:0] CLS_USABLE       = 4'd0;
       localparam logic [3:0] CLS_GENERAL_CALL = 4'd1;   // 0000000 + W
       localparam logic [3:0] CLS_START_BYTE   = 4'd2;   // 0000000 + R
       localparam logic [3:0] CLS_CBUS         = 4'd3;   // 0000001 + X
       localparam logic [3:0] CLS_OTHER_BUS    = 4'd4;   // 0000010 + X
       localparam logic [3:0] CLS_FUTURE       = 4'd5;   // 0000011 + X
       localparam logic [3:0] CLS_HS_MASTER    = 4'd6;   // 00001XX + X
       localparam logic [3:0] CLS_DEVICE_ID    = 4'd7;   // 11111XX + R
       localparam logic [3:0] CLS_TENBIT       = 4'd8;   // 11110XX + X
       localparam logic [3:0] CLS_RSVD_UPPER   = 4'd9;   // 11111XX + W -- reserved group,
                                                         // no purpose assigned by Table 3

       // Reservation is a property of the ADDRESS GROUP, not of the direction bit:
       // "Two groups of eight addresses (0000XXX and 1111XXX) are reserved."
       // The R/W bit then selects among purposes WITHIN an entry -- which is why
       // general call and START byte share one address and differ only in direction.
       assign is_reserved = (addr[6:3] == 4'b0000) || (addr[6:3] == 4'b1111);

       // The decode is written as a casez over the whole eight-bit byte so that it
       // reads as a transcription of Table 3 rather than as a chain of bit tests.
       // The don't-care positions are exactly the table's X columns.
       always_comb begin
           casez ({addr, rw})
               8'b0000000_0: addr_class = CLS_GENERAL_CALL;   // general call address
               8'b0000000_1: addr_class = CLS_START_BYTE;     // START byte
               8'b0000001_?: addr_class = CLS_CBUS;           // CBUS address
               8'b0000010_?: addr_class = CLS_OTHER_BUS;      // different bus format
               8'b0000011_?: addr_class = CLS_FUTURE;         // reserved for future use
               8'b00001??_?: addr_class = CLS_HS_MASTER;      // Hs-mode master code
               8'b11110??_?: addr_class = CLS_TENBIT;         // 10-bit slave addressing
               8'b11111??_1: addr_class = CLS_DEVICE_ID;      // device ID
               8'b11111??_0: addr_class = CLS_RSVD_UPPER;     // reserved group, no purpose
               default:      addr_class = CLS_USABLE;         // the other 112 addresses
           endcase
       end

       // Two footnotes in Table 3 are prohibitions rather than descriptions, and a
       // compliant device has to obey them in hardware:
       //   START byte  -- "No device is allowed to acknowledge at the reception of
       //                   the START byte."
       //   CBUS address -- "I2C-bus compatible devices are not allowed to respond on
       //                   reception of this address."
       assign must_not_ack = (addr_class == CLS_START_BYTE) || (addr_class == CLS_CBUS);
   endmodule

   module i2c_address_classifier_tb;
       localparam logic [3:0] CLS_USABLE       = 4'd0;
       localparam logic [3:0] CLS_GENERAL_CALL = 4'd1;
       localparam logic [3:0] CLS_START_BYTE   = 4'd2;
       localparam logic [3:0] CLS_CBUS         = 4'd3;
       localparam logic [3:0] CLS_OTHER_BUS    = 4'd4;
       localparam logic [3:0] CLS_FUTURE       = 4'd5;
       localparam logic [3:0] CLS_HS_MASTER    = 4'd6;
       localparam logic [3:0] CLS_DEVICE_ID    = 4'd7;
       localparam logic [3:0] CLS_TENBIT       = 4'd8;
       localparam logic [3:0] CLS_RSVD_UPPER   = 4'd9;

       logic [6:0] addr;
       logic       rw;
       logic       is_reserved;
       logic [3:0] addr_class;
       logic       must_not_ack;

       i2c_address_classifier dut (.*);

       int errors = 0;
       int n_reserved_addr = 0;
       int n_usable_addr   = 0;
       int class_hist [0:9];
       // Module scope: an initialised declaration inside a loop block is static in
       // SystemVerilog, and overriding the lifetime is not portable across tools.
       int usable_both;

       initial begin #20000; $display("FAIL: watchdog expired"); $finish; end

       // INDEPENDENT reference model. Deliberately written as arithmetic range tests
       // rather than as a bit-pattern case, so that a shared misreading of the table
       // cannot make model and design agree. Two implementations of the same table.
       function automatic logic [3:0] ref_class(input int a, input int d);
           if (a == 0)                    return (d == 1) ? CLS_START_BYTE : CLS_GENERAL_CALL;
           else if (a == 1)               return CLS_CBUS;
           else if (a == 2)               return CLS_OTHER_BUS;
           else if (a == 3)               return CLS_FUTURE;
           else if (a >= 4  && a <= 7)    return CLS_HS_MASTER;      // 00001XX
           else if (a >= 120 && a <= 123) return CLS_TENBIT;         // 11110XX = 0x78..0x7B
           else if (a >= 124 && a <= 127) return (d == 1) ? CLS_DEVICE_ID : CLS_RSVD_UPPER;
           else                           return CLS_USABLE;
       endfunction

       function automatic logic ref_reserved(input int a);
           // Reservation is by address group, independent of direction.
           return (a <= 7) || (a >= 120);
       endfunction

       initial begin
           for (int i = 0; i <= 9; i++) class_hist[i] = 0;

           // Exhaustive: every one of the 128 addresses, in both directions.
           for (int a = 0; a < 128; a++) begin
               usable_both = 1;
               for (int d = 0; d < 2; d++) begin
                   addr = a[6:0];
                   rw   = d[0];
                   #1;
                   if (addr_class !== ref_class(a, d)) begin
                       $display("FAIL: addr=0x%02h rw=%0b -- class %0d, reference says %0d",
                                a, d, addr_class, ref_class(a, d));
                       errors++;
                   end
                   if (is_reserved !== ref_reserved(a)) begin
                       $display("FAIL: addr=0x%02h -- is_reserved %0b, reference says %0b",
                                a, is_reserved, ref_reserved(a));
                       errors++;
                   end
                   // must_not_ack is normative: exactly the START byte and CBUS.
                   if (must_not_ack !== ((ref_class(a,d) == CLS_START_BYTE) ||
                                         (ref_class(a,d) == CLS_CBUS))) begin
                       $display("FAIL: addr=0x%02h rw=%0b -- must_not_ack wrong", a, d);
                       errors++;
                   end
                   class_hist[addr_class]++;
                   if (addr_class != CLS_USABLE) usable_both = 0;
               end
               if (ref_reserved(a)) n_reserved_addr++;
               if (usable_both)     n_usable_addr++;
           end

           // The address-space arithmetic, verified by counting rather than asserted.
           if (n_reserved_addr != 16) begin
               $display("FAIL: %0d reserved addresses, expected 16 (two groups of eight)", n_reserved_addr);
               errors++;
           end
           if (n_usable_addr != 112) begin
               $display("FAIL: %0d usable addresses, expected 112 (128 - 16)", n_usable_addr);
               errors++;
           end
           // Every reserved entry must be claimed by some purpose -- no reserved
           // address may fall through to CLS_USABLE.
           if (class_hist[CLS_USABLE] != 112 * 2) begin
               $display("FAIL: %0d usable classifications, expected %0d", class_hist[CLS_USABLE], 112*2);
               errors++;
           end
           // The two single-address, direction-selected entries occur exactly once each.
           if (class_hist[CLS_GENERAL_CALL] != 1 || class_hist[CLS_START_BYTE] != 1) begin
               $display("FAIL: general call / START byte must be one combination each (%0d / %0d)",
                        class_hist[CLS_GENERAL_CALL], class_hist[CLS_START_BYTE]);
               errors++;
           end
           // 11110XX spans four addresses, both directions.
           if (class_hist[CLS_TENBIT] != 8) begin
               $display("FAIL: 10-bit prefix should cover 8 combinations, got %0d", class_hist[CLS_TENBIT]);
               errors++;
           end

           if (errors == 0)
               $display("PASS: all 256 combinations match an independent model; %0d reserved, %0d usable addresses",
                        n_reserved_addr, n_usable_addr);
           else $display("FAIL: %0d error(s)", errors);
           $finish;
       end
   endmodule

   // Purely combinational decode of the reserved-address map. Encodes UM10204
   // Table 3 and the two footnotes that FORBID a device from responding.
   module i2c_address_classifier (
       input  wire [6:0] addr,          // the seven address bits
       input  wire       rw,            // the eighth bit on the wire
       output wire       is_reserved,   // the ADDRESS lies in a reserved group
       output reg  [3:0] addr_class,    // the specific purpose, see localparams
       output wire       must_not_ack   // the specification forbids responding
   );
       localparam [3:0] CLS_USABLE       = 4'd0;
       localparam [3:0] CLS_GENERAL_CALL = 4'd1;   // 0000000 + W
       localparam [3:0] CLS_START_BYTE   = 4'd2;   // 0000000 + R
       localparam [3:0] CLS_CBUS         = 4'd3;   // 0000001 + X
       localparam [3:0] CLS_OTHER_BUS    = 4'd4;   // 0000010 + X
       localparam [3:0] CLS_FUTURE       = 4'd5;   // 0000011 + X
       localparam [3:0] CLS_HS_MASTER    = 4'd6;   // 00001XX + X
       localparam [3:0] CLS_DEVICE_ID    = 4'd7;   // 11111XX + R
       localparam [3:0] CLS_TENBIT       = 4'd8;   // 11110XX + X
       localparam [3:0] CLS_RSVD_UPPER   = 4'd9;   // 11111XX + W

       // Reservation is a property of the ADDRESS GROUP, not of the direction bit.
       assign is_reserved = (addr[6:3] == 4'b0000) || (addr[6:3] == 4'b1111);

       // Written as a casez over the whole byte so it reads as a transcription of
       // Table 3; the don't-care positions are exactly the table's X columns.
       always @* begin
           casez ({addr, rw})
               8'b0000000_0: addr_class = CLS_GENERAL_CALL;   // general call address
               8'b0000000_1: addr_class = CLS_START_BYTE;     // START byte
               8'b0000001_?: addr_class = CLS_CBUS;           // CBUS address
               8'b0000010_?: addr_class = CLS_OTHER_BUS;      // different bus format
               8'b0000011_?: addr_class = CLS_FUTURE;         // reserved for future use
               8'b00001??_?: addr_class = CLS_HS_MASTER;      // Hs-mode master code
               8'b11110??_?: addr_class = CLS_TENBIT;         // 10-bit slave addressing
               8'b11111??_1: addr_class = CLS_DEVICE_ID;      // device ID
               8'b11111??_0: addr_class = CLS_RSVD_UPPER;     // reserved group, no purpose
               default:      addr_class = CLS_USABLE;         // the other 112 addresses
           endcase
       end

       // Two footnotes are prohibitions rather than descriptions:
       //   START byte   -- no device is allowed to acknowledge it
       //   CBUS address -- I2C-bus devices are not allowed to respond to it
       assign must_not_ack = (addr_class == CLS_START_BYTE) || (addr_class == CLS_CBUS);
   endmodule

   module i2c_address_classifier_tb;
       localparam [3:0] CLS_USABLE       = 4'd0;
       localparam [3:0] CLS_GENERAL_CALL = 4'd1;
       localparam [3:0] CLS_START_BYTE   = 4'd2;
       localparam [3:0] CLS_CBUS         = 4'd3;
       localparam [3:0] CLS_OTHER_BUS    = 4'd4;
       localparam [3:0] CLS_FUTURE       = 4'd5;
       localparam [3:0] CLS_HS_MASTER    = 4'd6;
       localparam [3:0] CLS_DEVICE_ID    = 4'd7;
       localparam [3:0] CLS_TENBIT       = 4'd8;
       localparam [3:0] CLS_RSVD_UPPER   = 4'd9;

       reg  [6:0] addr;
       reg        rw;
       wire       is_reserved;
       wire [3:0] addr_class;
       wire       must_not_ack;

       i2c_address_classifier dut (.addr(addr), .rw(rw), .is_reserved(is_reserved),
           .addr_class(addr_class), .must_not_ack(must_not_ack));

       integer errors, n_reserved_addr, n_usable_addr, usable_both, a, d, i;
       integer class_hist [0:9];

       initial begin #20000; $display("FAIL: watchdog expired"); $finish; end

       // INDEPENDENT reference model: arithmetic range tests rather than a bit-pattern
       // case, so a shared misreading cannot make model and design agree.
       function [3:0] ref_class; input integer a; input integer d; begin
           if (a == 0)                         ref_class = (d == 1) ? CLS_START_BYTE : CLS_GENERAL_CALL;
           else if (a == 1)                    ref_class = CLS_CBUS;
           else if (a == 2)                    ref_class = CLS_OTHER_BUS;
           else if (a == 3)                    ref_class = CLS_FUTURE;
           else if (a >= 4   && a <= 7)        ref_class = CLS_HS_MASTER;
           else if (a >= 120 && a <= 123)      ref_class = CLS_TENBIT;
           else if (a >= 124 && a <= 127)      ref_class = (d == 1) ? CLS_DEVICE_ID : CLS_RSVD_UPPER;
           else                                ref_class = CLS_USABLE;
       end endfunction

       function ref_reserved; input integer a; begin
           ref_reserved = (a <= 7) || (a >= 120);
       end endfunction

       initial begin
           errors = 0; n_reserved_addr = 0; n_usable_addr = 0;
           for (i = 0; i <= 9; i = i + 1) class_hist[i] = 0;

           for (a = 0; a < 128; a = a + 1) begin
               usable_both = 1;
               for (d = 0; d < 2; d = d + 1) begin
                   addr = a[6:0];
                   rw   = d[0];
                   #1;
                   if (addr_class !== ref_class(a, d)) begin
                       $display("FAIL: addr=0x%02h rw=%0b -- class %0d, reference says %0d",
                                a, d, addr_class, ref_class(a, d));
                       errors = errors + 1;
                   end
                   if (is_reserved !== ref_reserved(a)) begin
                       $display("FAIL: addr=0x%02h -- is_reserved %0b, reference says %0b",
                                a, is_reserved, ref_reserved(a));
                       errors = errors + 1;
                   end
                   if (must_not_ack !== ((ref_class(a,d) == CLS_START_BYTE) ||
                                         (ref_class(a,d) == CLS_CBUS))) begin
                       $display("FAIL: addr=0x%02h rw=%0b -- must_not_ack wrong", a, d);
                       errors = errors + 1;
                   end
                   class_hist[addr_class] = class_hist[addr_class] + 1;
                   if (addr_class != CLS_USABLE) usable_both = 0;
               end
               if (ref_reserved(a)) n_reserved_addr = n_reserved_addr + 1;
               if (usable_both)     n_usable_addr   = n_usable_addr + 1;
           end

           if (n_reserved_addr != 16) begin
               $display("FAIL: %0d reserved addresses, expected 16", n_reserved_addr); errors = errors + 1; end
           if (n_usable_addr != 112) begin
               $display("FAIL: %0d usable addresses, expected 112", n_usable_addr); errors = errors + 1; end
           if (class_hist[CLS_USABLE] != 112 * 2) begin
               $display("FAIL: %0d usable classifications, expected %0d", class_hist[CLS_USABLE], 112*2);
               errors = errors + 1; end
           if (class_hist[CLS_GENERAL_CALL] != 1 || class_hist[CLS_START_BYTE] != 1) begin
               $display("FAIL: general call / START byte must be one combination each");
               errors = errors + 1; end
           if (class_hist[CLS_TENBIT] != 8) begin
               $display("FAIL: 10-bit prefix should cover 8 combinations, got %0d", class_hist[CLS_TENBIT]);
               errors = errors + 1; end

           if (errors == 0)
               $display("PASS: all 256 combinations match an independent model; %0d reserved, %0d usable addresses",
                        n_reserved_addr, n_usable_addr);
           else $display("FAIL: %0d error(s)", errors);
           $finish;
       end
   endmodule

   library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;

   -- Purely combinational decode of the reserved-address map. Encodes UM10204
   -- Table 3 and the two footnotes that FORBID a device from responding.
   entity i2c_address_classifier is
       port (
           addr         : in  std_logic_vector(6 downto 0);  -- the seven address bits
           rw           : in  std_logic;                     -- the eighth bit on the wire
           is_reserved  : out std_logic;                     -- ADDRESS in a reserved group
           addr_class   : out std_logic_vector(3 downto 0);  -- the specific purpose
           must_not_ack : out std_logic                      -- spec forbids responding
       );
   end entity;

   architecture rtl of i2c_address_classifier is
       constant CLS_USABLE       : std_logic_vector(3 downto 0) := x"0";
       constant CLS_GENERAL_CALL : std_logic_vector(3 downto 0) := x"1";  -- 0000000 + W
       constant CLS_START_BYTE   : std_logic_vector(3 downto 0) := x"2";  -- 0000000 + R
       constant CLS_CBUS         : std_logic_vector(3 downto 0) := x"3";  -- 0000001 + X
       constant CLS_OTHER_BUS    : std_logic_vector(3 downto 0) := x"4";  -- 0000010 + X
       constant CLS_FUTURE       : std_logic_vector(3 downto 0) := x"5";  -- 0000011 + X
       constant CLS_HS_MASTER    : std_logic_vector(3 downto 0) := x"6";  -- 00001XX + X
       constant CLS_DEVICE_ID    : std_logic_vector(3 downto 0) := x"7";  -- 11111XX + R
       constant CLS_TENBIT       : std_logic_vector(3 downto 0) := x"8";  -- 11110XX + X
       constant CLS_RSVD_UPPER   : std_logic_vector(3 downto 0) := x"9";  -- 11111XX + W

       signal byte_on_wire : std_logic_vector(7 downto 0);
       signal cls          : std_logic_vector(3 downto 0);
   begin
       byte_on_wire <= addr & rw;

       -- Reservation is a property of the ADDRESS GROUP, not of the direction bit.
       is_reserved <= '1' when (addr(6 downto 3) = "0000" or addr(6 downto 3) = "1111")
                      else '0';

       -- VHDL-2008 matching case: '-' is a don't-care, so this reads as a direct
       -- transcription of Table 3, exactly as the casez versions do.
       process (byte_on_wire)
       begin
           case? byte_on_wire is
               when "0000000" & "0" => cls <= CLS_GENERAL_CALL;   -- general call address
               when "0000000" & "1" => cls <= CLS_START_BYTE;     -- START byte
               when "0000001-"      => cls <= CLS_CBUS;           -- CBUS address
               when "0000010-"      => cls <= CLS_OTHER_BUS;      -- different bus format
               when "0000011-"      => cls <= CLS_FUTURE;         -- reserved for future use
               when "00001---"      => cls <= CLS_HS_MASTER;      -- Hs-mode master code
               when "11110---"      => cls <= CLS_TENBIT;         -- 10-bit slave addressing
               when "11111--1"      => cls <= CLS_DEVICE_ID;      -- device ID
               when "11111--0"      => cls <= CLS_RSVD_UPPER;     -- reserved, no purpose
               when others          => cls <= CLS_USABLE;         -- the other 112 addresses
           end case?;
       end process;

       addr_class <= cls;

       -- Two footnotes are prohibitions rather than descriptions:
       --   START byte   -- no device is allowed to acknowledge it
       --   CBUS address -- I2C-bus devices are not allowed to respond to it
       must_not_ack <= '1' when (cls = CLS_START_BYTE or cls = CLS_CBUS) else '0';
   end architecture;

   library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;

   entity i2c_address_classifier_tb is
   end entity;

   architecture sim of i2c_address_classifier_tb is
       constant CLS_USABLE       : std_logic_vector(3 downto 0) := x"0";
       constant CLS_GENERAL_CALL : std_logic_vector(3 downto 0) := x"1";
       constant CLS_START_BYTE   : std_logic_vector(3 downto 0) := x"2";
       constant CLS_CBUS         : std_logic_vector(3 downto 0) := x"3";
       constant CLS_OTHER_BUS    : std_logic_vector(3 downto 0) := x"4";
       constant CLS_FUTURE       : std_logic_vector(3 downto 0) := x"5";
       constant CLS_HS_MASTER    : std_logic_vector(3 downto 0) := x"6";
       constant CLS_DEVICE_ID    : std_logic_vector(3 downto 0) := x"7";
       constant CLS_TENBIT       : std_logic_vector(3 downto 0) := x"8";
       constant CLS_RSVD_UPPER   : std_logic_vector(3 downto 0) := x"9";

       signal addr         : std_logic_vector(6 downto 0) := (others => '0');
       signal rw           : std_logic := '0';
       signal is_reserved  : std_logic;
       signal addr_class   : std_logic_vector(3 downto 0);
       signal must_not_ack : std_logic;
       signal test_done    : std_logic := '0';
   begin
       dut : entity work.i2c_address_classifier
           port map (addr => addr, rw => rw, is_reserved => is_reserved,
                     addr_class => addr_class, must_not_ack => must_not_ack);

       watchdog : process
       begin
           wait for 20 us;
           if test_done = '0' then
               report "watchdog expired -- the sweep never completed" severity failure;
           end if;
           wait;
       end process;

       stim : process
           variable errs            : natural := 0;
           variable n_reserved_addr : natural := 0;
           variable n_usable_addr   : natural := 0;
           variable usable_both     : boolean;
           type hist_t is array (0 to 9) of natural;
           variable class_hist      : hist_t := (others => 0);

           -- INDEPENDENT reference model: arithmetic range tests rather than a
           -- bit-pattern case, so a shared misreading cannot make the two agree.
           function ref_class (a : natural; d : natural) return std_logic_vector is
           begin
               if a = 0 then
                   if d = 1 then return CLS_START_BYTE; else return CLS_GENERAL_CALL; end if;
               elsif a = 1                   then return CLS_CBUS;
               elsif a = 2                   then return CLS_OTHER_BUS;
               elsif a = 3                   then return CLS_FUTURE;
               elsif a >= 4   and a <= 7     then return CLS_HS_MASTER;
               elsif a >= 120 and a <= 123   then return CLS_TENBIT;
               elsif a >= 124 and a <= 127   then
                   if d = 1 then return CLS_DEVICE_ID; else return CLS_RSVD_UPPER; end if;
               else                               return CLS_USABLE;
               end if;
           end function;

           function ref_reserved (a : natural) return std_logic is
           begin
               -- Reservation is by address group, independent of direction.
               if a <= 7 or a >= 120 then return '1'; else return '0'; end if;
           end function;
       begin
           for a in 0 to 127 loop
               usable_both := true;
               for d in 0 to 1 loop
                   addr <= std_logic_vector(to_unsigned(a, 7));
                   if d = 1 then rw <= '1'; else rw <= '0'; end if;
                   wait for 1 ns;

                   if addr_class /= ref_class(a, d) then
                       report "addr=" & integer'image(a) & " rw=" & integer'image(d)
                            & ": class disagrees with the reference model" severity error;
                       errs := errs + 1;
                   end if;
                   if is_reserved /= ref_reserved(a) then
                       report "addr=" & integer'image(a) & ": is_reserved disagrees" severity error;
                       errs := errs + 1;
                   end if;
                   if (must_not_ack = '1') /= (ref_class(a,d) = CLS_START_BYTE
                                            or ref_class(a,d) = CLS_CBUS) then
                       report "addr=" & integer'image(a) & " rw=" & integer'image(d)
                            & ": must_not_ack wrong" severity error;
                       errs := errs + 1;
                   end if;

                   class_hist(to_integer(unsigned(addr_class)))
                       := class_hist(to_integer(unsigned(addr_class))) + 1;
                   if addr_class /= CLS_USABLE then usable_both := false; end if;
               end loop;
               if ref_reserved(a) = '1' then n_reserved_addr := n_reserved_addr + 1; end if;
               if usable_both then n_usable_addr := n_usable_addr + 1; end if;
           end loop;

           if n_reserved_addr /= 16 then
               report "reserved addresses = " & integer'image(n_reserved_addr) & ", expected 16"
                   severity error; errs := errs + 1; end if;
           if n_usable_addr /= 112 then
               report "usable addresses = " & integer'image(n_usable_addr) & ", expected 112"
                   severity error; errs := errs + 1; end if;
           if class_hist(0) /= 224 then
               report "usable classifications = " & integer'image(class_hist(0)) & ", expected 224"
                   severity error; errs := errs + 1; end if;
           if class_hist(1) /= 1 or class_hist(2) /= 1 then
               report "general call / START byte must be one combination each" severity error;
               errs := errs + 1; end if;
           if class_hist(8) /= 8 then
               report "10-bit prefix should cover 8 combinations" severity error;
               errs := errs + 1; end if;

           if errs = 0 then
               report "i2c_address_classifier self-check complete: all 256 combinations match an "
                    & "independent model; " & integer'image(n_reserved_addr) & " reserved, "
                    & integer'image(n_usable_addr) & " usable addresses" severity note;
           else
               report "i2c_address_classifier self-check FAILED" severity error;
           end if;
           test_done <= '1';
           wait;
       end process;
   end architecture;

   // Normal traffic never sends a reserved address, so a constrained-random
   // sequence weighted towards realism will never test any of this chapter.
   // The reserved cases have to be a DELIBERATE sequence.
   class i2c_reserved_addr_seq extends uvm_sequence #(i2c_addr_phase);
       `uvm_object_utils(i2c_reserved_addr_seq)
       function new(string name = "i2c_reserved_addr_seq"); super.new(name); endfunction

       task body();
           i2c_addr_phase t;
           // Every reserved combination, not a sample of them: the space is 16
           // addresses by 2 directions, which is 32 transfers. Cheap, and complete.
           for (int a = 0; a < 128; a++) begin
               if (!(a <= 7 || a >= 120)) continue;       // only the reserved groups
               for (int d = 0; d < 2; d++) begin
                   t = i2c_addr_phase::type_id::create("t");
                   start_item(t);
                   t.addr = a[6:0];
                   t.read = d[0];
                   finish_item(t);
               end
           end
       endtask
   endclass

   // The checks these transfers feed are all NEGATIVE, and the assertion is the
   // natural form for a "must never" requirement.
   property no_ack_on_start_byte;
       @(posedge scl_rising) disable iff (!rst_n)
       (addr_phase_done && addr_seen == 7'b0000000 && rw_seen == 1'b1)
           |-> !any_device_acked;
   endproperty
   assert property (no_ack_on_start_byte)
       else `uvm_error("I2C_RSVD", "a device acknowledged the START byte")

   property no_ack_on_cbus;
       @(posedge scl_rising) disable iff (!rst_n)
       (addr_phase_done && addr_seen == 7'b0000001) |-> !any_device_acked;
   endproperty