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Ethernet · Module 3

Differential Signalling and the Analog Channel

A PHY does not read bits off a wire — it infers symbols from a waveform the channel has attenuated, reflected and smeared into its neighbours. Differential signalling, impedance, jitter and the eye are one subject: what margin is left after the channel takes its share.

Chapter 3.1 and Chapter 3.2 both stopped at the same place. Copper named attenuation, reflections and inter-symbol interference and pointed forward. Fibre named dispersion and did the same. Both were describing one subject from two sides.

Here it is, stated directly. Every digital abstraction above the PMD rests on a claim that turns out to be false: that a transmitted one arrives as a one.

It does not. A transmitter launches a voltage step. What reaches the far end is smaller — often by a factor of ten or more. It is slower, because the channel passes low frequencies better than high ones and an edge is made of high frequencies. It arrives at a time that varies from symbol to symbol. It carries delayed copies of itself from every impedance discontinuity along the way. And it is still carrying the tail of the symbol before it, and the one before that.

The receiver never sees a one. It sees a continuous voltage, and it must decide — at a moment it chose, against a threshold it chose — what was most likely sent.

What does a real channel do to a transmitted symbol, and what margin does the receiver have left to decide with?

1. Scope — What This Chapter Owns

This chapter owns: the exact decomposition of a differential pair into differential and common-mode components, what a receiver actually responds to, common-mode rejection and its two limits, characteristic impedance and reflections, frequency-dependent loss, inter-symbol interference and channel memory, jitter and its decomposition, the eye as a two-axis margin budget, and the boundary between what RTL can model, what behavioural verification can approximate, and what requires measurement.

This chapter does not own: equalisation as a design discipline. It names equalisation as the response to inter-symbol interference and shows the problem precisely, because you cannot understand a solution to a problem you have not seen — but feed-forward and decision-feedback architectures, tap adaptation and their trade-offs are a separate subject. Nor does it own line modulation: how many levels a symbol carries and what that does to margin is Chapter 3.6.

Every number in this chapter is either derived from a stated formula or explicitly labelled illustrative. No normative electrical limit from any IEEE clause is quoted, because those are clause-specific, revision-specific, and belong in the standard. Section 10 makes the distinction explicit and keeps it.

2. The Exact Model — Two Signals, Two Components

A differential pair carries two voltages, call them V-plus and V-minus, each measured against a shared reference. Any pair of voltages decomposes exactly into two components:

Differential-mode voltage: Vdiff = Vp − Vn

Common-mode voltage: Vcm = (Vp + Vn) / 2

The decomposition is invertible and loses nothing: Vp = Vcm + Vdiff/2 and Vn = Vcm − Vdiff/2. Two voltages, two components — this is a change of coordinates, not an approximation.

Two conductor voltages feed a decomposition into a differential component, which is their difference, and a common-mode component, which is their average. The receiver's amplifier responds to the differential component. External interference couples into the common-mode component, where the receiver rejects it. Excess common mode still reaches the receiver's input range limit.V-plusone conductorDifferentialthe difference of the twoReceiver amplifierresponds to this aloneDecisioncompare against athresholdV-minusthe other conductorCommon modethe average of the twoInput range limitthe rejection is notunlimitedthe signal12
Figure 1 — the same two voltages, seen in the coordinates the receiver uses.

Now the point of the coordinates. External interference — a nearby switching supply, a motor, a radio transmitter, a neighbouring cable — couples into a twisted pair almost equally on both conductors, because the twisting of Chapter 3.1 makes their exposure to any external field nearly identical.

Add the same disturbance n to both:

  • Vdiff becomes (Vp + n) − (Vn + n) = Vp − Vncompletely unchanged.
  • Vcm becomes Vcm + n — the disturbance lands here, entirely.

The receiver responds to Vdiff. So an interference source that would have swamped a single-ended signal referenced to ground has, in the differential coordinates, contributed exactly nothing to the quantity being measured. The noise did not get smaller. It moved into the coordinate nobody is looking at.

That is the whole mechanism, and it is why the rest of this chapter's impairments matter so much: differential signalling removes the largest and most variable noise source so cheaply that everything left is dominated by what the channel itself does — which is deterministic, and therefore correctable.

3. Common-Mode Rejection, and Its Two Limits

Section 2's cancellation is exact only if two conditions hold, and neither is free. Both fail in real designs, and knowing how they fail is what separates understanding the mechanism from reciting it.

Limit one — the rejection depends on balance. The cancellation assumed the disturbance appears equally on both conductors and that the receiver subtracts with equal weight. Any asymmetry breaks it: a length mismatch between the two traces of a pair, a via on one side and not the other, a gain imbalance in the receiver's input stage. Any of these converts a fraction of the common-mode disturbance into differential signal — which is indistinguishable from data, because the receiver's entire definition of data is the differential component.

Common-mode rejection ratio quantifies exactly this: how much larger a common-mode disturbance must be than a differential one to produce the same output. It is finite, it degrades with frequency, and it is a property of the whole path — cable, connector, package, and the receiver's own input stage — not of the receiver alone.

Limit two — rejection is not immunity. A receiver amplifier has an input range. Push the common-mode voltage far enough outside it and the input stage stops behaving linearly. At that point it is not rejecting anything, and the beautiful subtraction of Section 2 stops applying entirely.

This is why Chapter 3.1's transformer matters twice over: it provides galvanic isolation and it breaks the DC path that would otherwise let two equipment grounds at different potentials impose an arbitrarily large common-mode offset on the receiver.

4. Impedance, Return Paths, and Why a Trace Is a Transmission Line

At low frequencies a wire is a wire. At the edge rates in a modern Ethernet link it is not, and the reason is a comparison worth making concrete.

A signal travels at a finite speed. In a dielectric of relative permittivity εr, the propagation velocity is approximately v = c / sqrt(εr).

Illustrative calculation. Take εr = 4.2, a representative value for common PCB laminate:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
v = 3.0e8 / sqrt(4.2) = 3.0e8 / 2.049 = 1.46e8 m/s
 
delay per inch = 0.0254 / 1.46e8 = 1.74e-10 s = about 174 ps/inch

This is illustrative, not normative. The actual value depends on the laminate, the layer stack, and whether the trace is stripline or microstrip. What matters is the order of magnitude: roughly 170 picoseconds per inch.

Now compare that against a symbol period. At 10.3125 GBd — the line rate of a 10GBASE-R link — the unit interval is:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
UI = 1 / 10.3125e9 = 9.70e-11 s = about 97 ps

A six-inch trace is about ten unit intervals long. Ten symbols are simultaneously in flight on that trace at any instant. There is no meaningful sense in which the two ends are "the same node", and the wire must be treated as a transmission line — a structure with a characteristic impedance that relates voltage to current as a wave propagates along it.

Where the return path comes in. A signal current must return to its source. On a controlled-impedance board it returns through the reference plane directly beneath the trace, following the path of least inductance — which is directly under the signal. The impedance is set by the geometry of the signal conductor relative to that return path. Interrupt the return — a split in the plane, a layer change with no nearby stitching via — and the return current is forced to detour, the local impedance changes, and a discontinuity has been created where the schematic shows a plain wire.

For a differential pair the relevant quantity is the differential impedance between the two conductors, and the same argument applies to both.

5. Reflections, Quantified

Wherever the impedance changes, part of the wave is reflected. The fraction is the reflection coefficient:

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Snippet
Gamma = (Z_load - Z_0) / (Z_load + Z_0)

Illustrative calculation. A 100-ohm differential channel meeting a 120-ohm discontinuity:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
Gamma = (120 - 100) / (120 + 100) = 20 / 220 = 0.091

About nine percent of the incident amplitude reflects — from a twenty-percent impedance error, which is not an unusual manufacturing or connector tolerance.

Why that nine percent is worse than it looks. The reflection travels back to the source, reflects again off whatever it finds there, and returns. It arrives at the receiver delayed by twice the distance to the discontinuity, which at 174 ps/inch means a discontinuity three inches away produces an echo about a full unit interval late at 10.3125 GBd — landing squarely on the next symbol.

Three consequences worth carrying:

  1. Reflections are differential. They are a copy of the wanted signal, so Section 2's rejection does nothing about them. This is one of the impairments the earlier callout named.
  2. Reflections are deterministic and pattern-dependent. The same data pattern produces the same reflection every time. That makes them correctable in principle — and it makes them distinguishable from random noise in practice, which Section 12 turns into working silicon.
  3. Every connector is a discontinuity. Chapter 3.1's observation that connectors dominate a short link's budget has its mechanism here: each mated connection is an impedance step, and each contributes a reflection.

6. Frequency-Dependent Loss, and Where Inter-Symbol Interference Comes From

The channel attenuates, and — this is the part that produces everything else in this section — it attenuates more at higher frequencies. Conductor loss rises with the square root of frequency; dielectric loss rises roughly linearly with it.

Why that reshapes a pulse rather than just shrinking it. A rectangular pulse is a sum of frequency components: low ones give it its body, high ones give it its sharp edges. Attenuate the high components more and the edges soften — the pulse rises more slowly, and its energy spreads beyond the symbol period it was supposed to occupy.

That spread-out energy lands on the following symbols. This is inter-symbol interference, and it is the single most important impairment in a modern high-rate link.

Property of ISIConsequence
it is signal, not noisedifferential rejection does nothing about it
it is deterministicthe same pattern produces the same interference every time
it is pattern-dependenta long run of one level biases the following symbols far more than an alternating pattern does
it consumes both marginsthe level at sampling is wrong and the crossing time moves

The third row is the diagnostic one, and it is the whole reason this section exists. Random noise is uncorrelated with the data. ISI is caused by the data. So if the errors on a link correlate with the preceding bit pattern, the cause is the channel's memory — and if they do not, it is noise or interference. That distinction is measurable in hardware, and Section 12 builds the block that measures it.

Channel memory is the general name for the phenomenon: the channel's output at any instant depends not only on the current symbol but on some number of preceding ones. A channel with memory of three symbols means the receiver's decision is contaminated by the three that came before.

The response is equalisation — applying an approximate inverse of the channel so the tails cancel. It works precisely because ISI is deterministic. This chapter stops at naming it; the architectures and their trade-offs are a separate subject, and Chapter 3.1 already showed where equaliser convergence appears at the digital interface as a training phase that must complete.

7. Jitter — and Why It Splits Into Two Kinds

Jitter is the deviation of a signal's transitions from their ideal times. It matters because a receiver samples at a chosen instant, and if the transitions move, the sampling instant is no longer where the design put it relative to the data.

Jitter divides into two categories with completely different mathematics, and the division is not academic — it determines how you budget.

Random jitterDeterministic jitter
Sourcethermal and shot noise in circuitsISI, reflections, crosstalk, supply coupling, duty-cycle error
DistributionGaussianbounded, often multi-modal
Peak valueunbounded — grows with observation timebounded — has a genuine maximum
Correlated with data?nooften yes
Reducible bybetter circuits, lower noisefixing the channel, or equalisation

The critical asymmetry is the "peak value" row. Deterministic jitter has a real worst case: observe long enough and you have seen it. Random jitter does not — a Gaussian distribution has no maximum, so the longer you watch, the larger the excursion you will eventually see.

Which means peak-to-peak random jitter is not a meaningful number without a probability attached. It is quoted at a bit error rate, and the standard construction is:

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Snippet
TJ(BER) = DJ + Q(BER) * RJ_rms

where RJ_rms is the standard deviation of the random component and Q(BER) is the multiplier that makes the Gaussian tails integrate to the target error rate.

Illustrative calculation. For a target bit error rate of 1e-12, the one-sided Gaussian tail requires about 7.03 standard deviations. Errors can occur on either side of the sampling point, so the total spread is roughly twice that:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
Q(1e-12) = about 14.07
 
With DJ = 20 ps and RJ_rms = 1.5 ps:
TJ = 20 + 14.07 * 1.5 = 20 + 21.1 = about 41 ps

Now put that against the unit interval. At 10.3125 GBd the UI is about 97 ps, so 41 ps of total jitter has consumed roughly 42 percent of the symbol period before the receiver has done anything at all.

These are illustrative figures chosen to show the arithmetic, not values from any standard. What is worth carrying is the shape of the result: the random term was small in isolation — 1.5 ps against 20 ps of deterministic jitter — and after multiplication by 14 it was the larger contributor. Random jitter is dangerous precisely because its raw number looks negligible.

8. The Eye — Two Margins, One Picture

Overlay many unit intervals of a received signal, aligned to the recovered clock. The transitions cluster at the edges, the stable levels cluster in the middle, and the open region between them is the eye.

Conceptual — the sampling window inside one unit interval

8 cycles
A conceptual timing diagram over eight symbol periods. The recovered clock defines the symbol boundaries. The transmitted data changes each period. The received signal is shown as uncertain during the transition regions at the start of each period and stable in the middle. Markers indicate the unit interval, the jitter-corrupted crossing regions, and the sampling instant at the centre of the eye.one unit intervalone unit intervalcrossings spread by jittercrossings spread by jittersample here — widest openingsample here — widestopeningmargin is what remainsmargin is what remainsrec_clktx_sym10010110rx_edgeXXXXXXXXrx_validt0t1t2t3t4t5t6t7
Figure 2 — conceptual: the sampling window is what is left after jitter takes both edges.

This diagram is conceptual and is labelled so. A real eye diagram is an analog measurement made on an oscilloscope with a persistence display; a digital waveform cannot represent overlaid analog traces. What it can show correctly, and what is shown here, is the relationship: the rx_edge row marks the regions where the received signal is uncertain because transitions land somewhere within them, and rx_valid is trustworthy only away from those regions.

The eye has exactly two dimensions, and they are consumed by different mechanisms:

DimensionWhat it isClosed by
Horizontal — eye widththe time span in which sampling gives the right answerjitter, slowed edges, ISI moving the crossings
Vertical — eye heightthe voltage separation between levels at the sampling instantattenuation, noise, crosstalk, residual echo, ISI biasing the level

Eye width, approximately: UI − TJ(BER). Using Section 7's illustrative figures, 97 ps minus 41 ps leaves about 56 ps of window — and the receiver must place its sampling point inside it and keep it there across temperature and supply variation.

Two facts about the eye that carry the most weight:

First, ISI closes it in both directions. Every other impairment is on one axis. ISI biases the level at the sampling instant and moves the crossing times, because both are consequences of the previous symbol's tail still being present. That double action is why it dominates at high rates.

Second, the eye is a property of a point in the system, not of a link. The eye at the transmitter's pins is wide open. At the receiver's package it is smaller. After the receiver's equaliser it may be open again — which is exactly the point of equalisation, and it is why measuring at an accessible point can show a closed eye on a link that works perfectly.

9. Where Margin Actually Goes

Bringing Sections 4 through 8 together as one budget, because the budget is the useful artefact.

Margin is consumed in stages. The transmitter launches a full-amplitude symbol over one unit interval. Frequency-dependent loss reduces amplitude and softens edges. Reflections add delayed copies. Crosstalk and residual echo add interference. Jitter spreads the crossing times. What remains after all of these is the margin the receiver decides with.From a launched symbol to a decision1Launched symbolfull amplitude, one unit interval2Loss reshapes itsmaller, softer edges, spread tail3Reflections add copiesdelayed, and differential4Coupling adds interferencecrosstalk and residual echo5Jitter moves the edgesrandom plus deterministic6What is left is marginthe receiver decides with this
Figure 3 — each stage takes its share, and only the remainder is margin.

Read stages 2 through 5 as the debugging partition, because each has a distinct signature:

StageSignatureDistinguishing test
loss and ISIerrors correlate with the data patterncompare error rate on a stressing pattern against an alternating one
reflectionserrors at a fixed delay from a transitionthe delay locates the discontinuity, at about 174 ps per inch, doubled
crosstalkerrors correlate with another channel's activityquiesce the neighbour and re-measure
jittererrors uncorrelated with data, and rate falls sharply as the sampling point movessweep the sampling phase

Every one of those tests is a measurement someone can actually make, and three of the four are measurable from inside the chip with the instrumentation Sections 11 and 12 build.

10. What Is Illustrative and What Is Normative

Stated once, explicitly, because getting this wrong in a design review is expensive.

Everything numeric in this chapter is one of two things:

Derived from a stated formula. UI = 1/symbol rate; Gamma = (Z_load − Z_0)/(Z_load + Z_0); v = c/sqrt(εr); TJ = DJ + Q·RJ_rms. These are relationships, and they hold wherever their assumptions do. The inputs used with them here — 4.2 for permittivity, 120 ohms for a discontinuity, 20 ps of deterministic jitter — are chosen to make arithmetic concrete and are explicitly labelled illustrative.

Nothing in this chapter is a normative Ethernet electrical requirement. No insertion-loss mask, no return-loss template, no jitter budget, no eye mask, no transmit amplitude envelope. Those exist, they are specific to a clause and a revision, and they are the sole authority when a design decision depends on one.

11. RTL 1 — The Slicer, and Where the Digital Domain Begins

Everything above this section is analog. This is where RTL starts, and the boundary is worth stating precisely: RTL begins after the decision has been made.

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
// SYNTHESIZABLE. Threshold decision over an already-digitised amplitude.
//
// This is the FIRST digital block in the receiver. Everything upstream is
// analog and is not represented anywhere in this file.
//
// The lesson: a decision is not just a comparison. A sample sitting near a
// threshold is a decision the receiver is not confident about, and a
// receiver that cannot say so has thrown away the most useful early warning
// it has -- confidence degrades long before the error rate rises.
module symbol_slicer #(
  parameter int unsigned SAMPLE_W = 8,   // signed digitised amplitude
  parameter int unsigned LEVELS   = 2,   // 2 for NRZ; 4 for PAM4
  parameter int unsigned SYM_W    = $clog2(LEVELS),
  // How close to a threshold counts as "not confident", in sample units.
  parameter int unsigned GUARD    = 8
) (
  input  logic clk,
  input  logic rst_n,
 
  input  logic                     sample_valid,
  input  logic signed [SAMPLE_W-1:0] sample,
 
  // Thresholds, supplied by the (unmodelled) adaptation loop. LEVELS-1 of
  // them, in ascending order. They are INPUTS: where they come from is an
  // analog and control-loop question, not an RTL one.
  input  logic signed [SAMPLE_W-1:0] threshold [LEVELS-1],
 
  output logic                 sym_valid,
  output logic [SYM_W-1:0]     symbol,
 
  // Confidence: the sample was within GUARD of the threshold it was decided
  // against. Not an error -- the decision may well be right -- but it means
  // the eye is closing at this sampling point.
  output logic                 low_confidence,
 
  // Distance from the nearest threshold, in sample units. This is a direct
  // digital proxy for VERTICAL EYE MARGIN, and it is available every symbol
  // with no test equipment attached.
  output logic [SAMPLE_W-1:0]  margin
);
 
  logic [SYM_W-1:0]            sym_c;
  logic signed [SAMPLE_W-1:0]  nearest_thr_c;
  logic [SAMPLE_W:0]           dist_c;
 
  always_comb begin
    // Count how many thresholds the sample exceeds. For NRZ that is one
    // comparison; for PAM4 it is three. Same structure either way.
    sym_c = '0;
    for (int unsigned t = 0; t < LEVELS-1; t++) begin
      if (sample > threshold[t]) sym_c = SYM_W'(t + 1);
    end
 
    // Distance to the nearest threshold, whichever it is.
    nearest_thr_c = threshold[0];
    dist_c        = '1;
    for (int unsigned t = 0; t < LEVELS-1; t++) begin
      automatic logic [SAMPLE_W:0] d =
        (sample > threshold[t]) ? (SAMPLE_W+1)'(sample - threshold[t])
                                : (SAMPLE_W+1)'(threshold[t] - sample);
      if (d < dist_c) begin
        dist_c        = d;
        nearest_thr_c = threshold[t];
      end
    end
  end
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      sym_valid      <= 1'b0;
      symbol         <= '0;
      low_confidence <= 1'b0;
      margin         <= '0;
    end else begin
      sym_valid <= sample_valid;
      if (sample_valid) begin
        symbol         <= sym_c;
        margin         <= dist_c[SAMPLE_W-1:0];
        low_confidence <= (dist_c < (SAMPLE_W+1)'(GUARD));
      end
    end
  end
 
endmodule

Classification: synthesizable.

What it teaches: that a decision carries a confidence, and that the confidence is free. The distance from the nearest threshold is a digital measurement of vertical eye margin, available every symbol, with no instrument connected. A design that outputs only the decided symbol has discarded it.

Deliberately simplified: thresholds are inputs. Real receivers adapt them continuously, and the adaptation loop is an analog and control-theory problem that RTL does not model. The number of levels is parameterised because the structure genuinely is the same for NRZ and PAM4 — but Chapter 3.6 owns what changing it costs in margin.

Production implication: margin is the most valuable output in the module and the one most often omitted. It degrades gradually and monotonically as a channel ages or heats, so it gives advance warning — while an error counter stays at zero right up until it does not. A link whose margin has halved over six months is failing, and no error-based metric can see it.

Later ownership: how many levels to use, and what each additional level costs in vertical margin, is Chapter 3.6.

12. RTL 2 — Detecting Channel Memory From Inside the Chip

Section 6 established the diagnostic fact: ISI errors correlate with the preceding data pattern; noise errors do not. That correlation is measurable in digital logic, and measuring it turns "this link errors sometimes" into "this link's channel has memory of two symbols" — which is a completely different conversation.

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
// SYNTHESIZABLE INSTRUMENTATION. Outside the datapath.
//
// The measurement: bin low-confidence decisions by the PRECEDING symbol
// pattern. If the bins are flat, the cause is uncorrelated -- noise,
// crosstalk, or interference. If some bins dominate, the channel has
// MEMORY, and which bins dominate says how much.
//
// This is the difference between "the link errors sometimes" and "this
// channel has two symbols of memory and needs more equalisation", and the
// second statement has an owner.
module channel_memory_monitor #(
  parameter int unsigned SYM_W   = 1,   // bits per symbol
  parameter int unsigned HISTORY = 2,   // preceding symbols to correlate on
  parameter int unsigned BINS    = 1 << (SYM_W * HISTORY),
  parameter int unsigned CNT_W   = 20
) (
  input  logic clk,
  input  logic rst_n,
  input  logic clear,
 
  input  logic             sym_valid,
  input  logic [SYM_W-1:0] symbol,
  input  logic             low_confidence,
 
  // One count per preceding-pattern bin.
  output logic [CNT_W-1:0] bin_count  [BINS],
  output logic [CNT_W-1:0] bin_events [BINS],
 
  // Set when one bin's event RATE is far above the mean. Strong evidence of
  // channel memory rather than of noise.
  output logic             memory_suspected,
  output logic [$clog2(BINS)-1:0] worst_bin
);
 
  logic [SYM_W*HISTORY-1:0] hist_q;
  logic [$clog2(BINS)-1:0]  bin_idx;
 
  assign bin_idx = hist_q[$clog2(BINS)-1:0];
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n || clear) begin
      for (int unsigned b = 0; b < BINS; b++) begin
        bin_count[b]  <= '0;
        bin_events[b] <= '0;
      end
      if (!rst_n) hist_q <= '0;
    end else if (sym_valid) begin
      // Bin THIS symbol's outcome against the pattern that PRECEDED it.
      // The ordering is the whole measurement: binning against the current
      // symbol would measure level-dependent error, which is a different
      // and much less useful thing.
      if (!(&bin_count[bin_idx]))  bin_count[bin_idx]  <= bin_count[bin_idx] + 1'b1;
      if (low_confidence && !(&bin_events[bin_idx]))
        bin_events[bin_idx] <= bin_events[bin_idx] + 1'b1;
 
      hist_q <= {hist_q[SYM_W*HISTORY-SYM_W-1:0], symbol};
    end
  end
 
  // A deliberately crude comparison: one bin carrying more than half of all
  // events. Cheap, and sufficient to raise the flag -- the precise
  // characterisation is software's job once the flag says to look.
  logic [CNT_W+2:0] total_events_c;
  logic [CNT_W-1:0] max_events_c;
  logic [$clog2(BINS)-1:0] max_bin_c;
 
  always_comb begin
    total_events_c = '0;
    max_events_c   = '0;
    max_bin_c      = '0;
    for (int unsigned b = 0; b < BINS; b++) begin
      total_events_c = total_events_c + (CNT_W+3)'(bin_events[b]);
      if (bin_events[b] > max_events_c) begin
        max_events_c = bin_events[b];
        max_bin_c    = ($clog2(BINS))'(b);
      end
    end
  end
 
  assign worst_bin        = max_bin_c;
  assign memory_suspected = (total_events_c != 0)
                         && ((CNT_W+3)'(max_events_c) * 2 > total_events_c);
 
endmodule

Classification: synthesizable instrumentation.

What it teaches: how to turn a statistical property of a channel into a hardware measurement. The binning order is the entire technique — this symbol's outcome, against the pattern that came before it. Bin against the current symbol instead and you measure level-dependent error, which is a real but different effect and does not answer the ISI question at all.

Deliberately simplified: two symbols of history and a crude majority test. Production implementations use deeper history and proper statistics, and often correlate against a downstream reference decision rather than a confidence flag.

Production implication: this block is the difference between a link that gets replaced and a link that gets fixed. Flat bins mean the cause is external — go looking for an interference source or a crosstalk aggressor. Peaked bins mean the channel has memory — the fix is equalisation, a shorter or better channel, or a lower rate, and no amount of shielding will help. Those two conclusions send two different teams in two different directions, and the block that separates them is a few hundred gates.

13. RTL 3 — Margin Telemetry

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
// SYNTHESIZABLE INSTRUMENTATION.
//
// Margin degrades gradually; errors appear suddenly. A design that reports
// only errors gives no warning at all -- the counter reads zero right up
// until the link stops working. Tracking the MINIMUM margin over a window
// gives months of warning on an ageing channel.
module margin_telemetry #(
  parameter int unsigned SAMPLE_W = 8,
  parameter int unsigned CNT_W    = 24,
  // Window length for the running minimum, in symbols.
  parameter int unsigned WINDOW   = 1_000_000,
  parameter int unsigned WIN_W    = $clog2(WINDOW + 1)
) (
  input  logic clk,
  input  logic rst_n,
  input  logic clear,
 
  input  logic                sym_valid,
  input  logic [SAMPLE_W-1:0] margin,
  input  logic                low_confidence,
  input  logic                symbol_error,     // from a downstream check
  input  logic                lock_lost,
 
  // Minimum margin observed in the window that just closed. This is the
  // number to trend: it falls long before symbol_error ever asserts.
  output logic [SAMPLE_W-1:0] window_min_margin,
  output logic                window_valid,
 
  // Worst ever seen since reset. Survives `clear` -- it is a property of
  // the installed channel, not of a chosen measurement window.
  output logic [SAMPLE_W-1:0] worst_ever_margin,
 
  output logic [CNT_W-1:0]    c_low_confidence,
  output logic [CNT_W-1:0]    c_symbol_error,
  output logic [CNT_W-1:0]    c_lock_lost,
 
  // Consecutive errors, which separates a burst from scattered singles.
  // Bursts point at reflections or an interference event; scattered singles
  // point at the noise floor. Different causes, different fixes.
  output logic [15:0]         longest_error_burst
);
 
  logic [SAMPLE_W-1:0] run_min_q;
  logic [WIN_W-1:0]    win_q;
  logic [15:0]         burst_q;
 
  function automatic logic [CNT_W-1:0] bump(input logic [CNT_W-1:0] v,
                                            input logic             en);
    bump = (en && !(&v)) ? (v + 1'b1) : v;
  endfunction
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      run_min_q           <= '1;
      win_q               <= '0;
      window_min_margin   <= '1;
      window_valid        <= 1'b0;
      worst_ever_margin   <= '1;
      c_low_confidence    <= '0;
      c_symbol_error      <= '0;
      c_lock_lost         <= '0;
      burst_q             <= '0;
      longest_error_burst <= '0;
    end else begin
      if (clear) begin
        c_low_confidence    <= '0;
        c_symbol_error      <= '0;
        c_lock_lost         <= '0;
        longest_error_burst <= '0;
        // worst_ever_margin deliberately NOT cleared.
      end else begin
        c_low_confidence <= bump(c_low_confidence, low_confidence && sym_valid);
        c_symbol_error   <= bump(c_symbol_error,   symbol_error);
        c_lock_lost      <= bump(c_lock_lost,      lock_lost);
      end
 
      if (sym_valid) begin
        if (margin < run_min_q)         run_min_q         <= margin;
        if (margin < worst_ever_margin) worst_ever_margin <= margin;
 
        if (win_q == WIN_W'(WINDOW - 1)) begin
          window_min_margin <= (margin < run_min_q) ? margin : run_min_q;
          window_valid      <= 1'b1;
          run_min_q         <= '1;    // start the next window clean
          win_q             <= '0;
        end else begin
          win_q <= win_q + 1'b1;
        end
 
        // Burst tracking.
        if (symbol_error) begin
          burst_q <= burst_q + 1'b1;
          if ((burst_q + 1'b1) > longest_error_burst)
            longest_error_burst <= burst_q + 1'b1;
        end else begin
          burst_q <= '0;
        end
      end
    end
  end
 
endmodule

Classification: synthesizable instrumentation.

What it teaches: that the useful margin metric is a minimum over a window, trended. An average hides the worst case, which is the only case that produces errors. A single reading has no context. The window minimum, plotted over weeks, shows a channel ageing before it fails.

Deliberately simplified: one window and one minimum. Production designs usually keep a histogram, which reveals the distribution rather than only its worst point.

Production implication: longest_error_burst is the cheapest useful discriminator in the module. Scattered single errors point at the noise floor — the eye is marginally closed and thermal noise occasionally crosses the threshold. Bursts point at a discrete event: a reflection arriving on a particular pattern, a crosstalk aggressor switching, a supply transient. Two causes, two investigations, one 16-bit register.

14. RTL 4 — Measuring the Other Axis

Section 11's margin measures the eye vertically. Section 8 established that the eye has two dimensions and that they are consumed by different mechanisms — so an instrument that reads only one of them is reporting half the budget.

The horizontal axis is measurable too, and by the same trick: sample the same data twice, once at the nominal point and once at a deliberately offset one, and compare. Where the offset sampler starts disagreeing is where the eye closes.

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
// SYNTHESIZABLE INSTRUMENTATION. Outside the datapath.
//
// Horizontal eye margin, measured from inside the chip.
//
// The method: a second sampler runs at a controllable phase offset from the
// data sampler. Where its decisions start diverging from the reference, the
// eye has closed. Sweep the offset and the divergence boundary IS the eye
// width -- no oscilloscope, no probe, and available on a link in service.
module eye_phase_scanner #(
  parameter int unsigned PHASE_STEPS = 32,   // offsets the interpolator offers
  parameter int unsigned PH_W        = $clog2(PHASE_STEPS),
  parameter int unsigned CNT_W       = 20,
  // Symbols to accumulate at each offset before the point is trusted.
  parameter int unsigned DWELL       = 100_000,
  parameter int unsigned DWELL_W     = $clog2(DWELL + 1),
  // Disagreements per dwell above which this offset is outside the eye.
  parameter int unsigned FAIL_THRESH = 16
) (
  input  logic clk,
  input  logic rst_n,
 
  input  logic scan_start,
 
  input  logic sym_valid,
  input  logic ref_symbol,      // decision at the nominal sampling point
  input  logic offset_symbol,   // decision at the offset sampling point
 
  // Request to the (unmodelled) phase interpolator.
  output logic [PH_W-1:0]  offset_phase,
 
  // One disagreement count per phase offset. The contiguous run of offsets
  // below FAIL_THRESH is the open eye.
  output logic [CNT_W-1:0] phase_errors [PHASE_STEPS],
 
  output logic             scan_done,
  output logic [PH_W-1:0]  eye_width_steps,  // widest contiguous passing run
  output logic [PH_W-1:0]  eye_centre_step   // middle of that run
);
 
  logic [PH_W-1:0]    phase_q;
  logic [DWELL_W-1:0] dwell_q;
  logic               scanning_q;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      for (int unsigned i = 0; i < PHASE_STEPS; i++) phase_errors[i] <= '0;
      phase_q    <= '0;
      dwell_q    <= '0;
      scanning_q <= 1'b0;
      scan_done  <= 1'b0;
    end else if (scan_start && !scanning_q) begin
      for (int unsigned i = 0; i < PHASE_STEPS; i++) phase_errors[i] <= '0;
      phase_q    <= '0;
      dwell_q    <= '0;
      scanning_q <= 1'b1;
      scan_done  <= 1'b0;
    end else if (scanning_q && sym_valid) begin
      // A disagreement between the two samplers, NOT an error in the data
      // path. The reference decision is the one the link actually uses; this
      // measurement never affects it.
      if (ref_symbol != offset_symbol) begin
        if (!(&phase_errors[phase_q]))
          phase_errors[phase_q] <= phase_errors[phase_q] + 1'b1;
      end
 
      if (dwell_q == DWELL_W'(DWELL - 1)) begin
        dwell_q <= '0;
        if (phase_q == PH_W'(PHASE_STEPS - 1)) begin
          scanning_q <= 1'b0;
          scan_done  <= 1'b1;
        end else begin
          phase_q <= phase_q + 1'b1;
        end
      end else begin
        dwell_q <= dwell_q + 1'b1;
      end
    end
  end
 
  assign offset_phase = phase_q;
 
  // Widest CONTIGUOUS run of passing offsets. Contiguity matters: a scan
  // with passing offsets on both edges and failures in the middle is not an
  // eye at all -- it is a broken measurement, most often a phase
  // interpolator that is not monotonic.
  logic [PH_W-1:0] run_c, best_c, best_end_c;
 
  always_comb begin
    run_c      = '0;
    best_c     = '0;
    best_end_c = '0;
    for (int unsigned i = 0; i < PHASE_STEPS; i++) begin
      if (phase_errors[i] < CNT_W'(FAIL_THRESH)) begin
        run_c = run_c + 1'b1;
        if (run_c > best_c) begin
          best_c     = run_c;
          best_end_c = PH_W'(i);
        end
      end else begin
        run_c = '0;
      end
    end
  end
 
  assign eye_width_steps = best_c;
  assign eye_centre_step = (best_c == 0) ? '0 : (best_end_c - (best_c >> 1));
 
endmodule

Classification: synthesizable instrumentation.

What it teaches: that horizontal margin is measurable in service, and that the measurement is a comparison between two samplers rather than an absolute quantity. The offset sampler's disagreements are not data errors — the reference decision is what the link uses, and the scan never touches it. That separation is what makes the instrument safe to run on production traffic.

Deliberately simplified: the phase interpolator is an input request. Its resolution sets the granularity of the answer and its linearity sets the answer's trustworthiness, and both are analog properties this model cannot represent.

Production implication: eye_centre_step is as valuable as the width. A scan that finds the eye open but the nominal sampling point sitting off-centre says the link works and has less margin than it should — a condition invisible to every other instrument, and one that turns into intermittent errors as soon as temperature moves the eye slightly. Re-centring costs nothing and recovers real margin.

And the contiguity check is not fussiness. Passing offsets on both edges of the scan with failures between them is not a narrow eye; it is a broken measurement, almost always a non-monotonic phase interpolator. A design that reports the widest run without requiring contiguity will confidently report a wide eye from nonsense data.

Later ownership: how sampling phase is chosen and maintained in normal operation belongs with clock recovery, which Chapter 2.6 introduced.

15. The Verification Model — What It Can and Cannot Claim

Section 10 drew the line between illustrative and normative. This one draws the line between simulation and measurement, and it is the more consequential of the two for a verification plan.

The questionWhat can answer it
does the slicer decide correctly against given thresholds?RTL simulation — fully
does confidence assert within the guard band?RTL simulation — fully
does the binning correlate against the preceding pattern?RTL simulation — fully
are the window minimum and burst tracking correct?RTL simulation — fully
does the link have enough margin at this rate on this channel?analog or mixed-signal simulation, then measurement
what is the eye height and width at the receiver's package?laboratory measurement — an oscilloscope
what is the total jitter at a bit error rate of 1e-12?laboratory measurement, over a long enough run to observe the tails
does the design meet a clause's eye mask?laboratory measurement, against the standard
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
// NON-SYNTHESIZABLE. VERIFICATION ONLY.
//
// ============================================================================
// THIS DOES NOT MODEL AN ANALOG CHANNEL.
//
// It reduces sample amplitude and skips or repeats samples so that the
// DIGITAL blocks -- slicer confidence, memory binning, margin telemetry --
// can be exercised. Attenuation, reflections, dispersion, real jitter
// distributions and equaliser behaviour are all absent. Nothing measured
// here predicts the behaviour of a physical link.
//
// Its one genuine claim: the ISI mode below is PATTERN-CORRELATED, so it
// exercises the correlation logic of Section 12 in the direction that logic
// is meant to detect.
// ============================================================================
module impairment_injector #(
  parameter int unsigned SAMPLE_W = 8
) (
  input  logic clk,
  input  logic rst_n,
 
  input  logic signed [SAMPLE_W-1:0] clean_sample,
  input  logic                       clean_valid,
 
  // Directed controls. Explicit rather than random: the point is to reach a
  // named condition, not to sample a distribution.
  input  logic                       en_attenuate,  // scale amplitude down
  input  logic [2:0]                 atten_shift,
  input  logic                       en_isi,        // pattern-correlated bias
  input  logic                       en_noise,      // uncorrelated offset
  input  logic signed [SAMPLE_W-1:0] noise_offset,
  input  logic                       en_skip,       // drop a sample: timing
 
  output logic signed [SAMPLE_W-1:0] dirty_sample,
  output logic                       dirty_valid
);
 
  logic signed [SAMPLE_W-1:0] prev_q;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)           prev_q <= '0;
    else if (clean_valid) prev_q <= clean_sample;
  end
 
  logic signed [SAMPLE_W-1:0] atten_c;
  logic signed [SAMPLE_W-1:0] isi_c;
 
  always_comb begin
    atten_c = en_attenuate ? (clean_sample >>> atten_shift) : clean_sample;
 
    // The ONLY part of this model that resembles a real mechanism: bias the
    // current sample toward the PREVIOUS one. That is what channel memory
    // does, and it is pattern-correlated by construction -- which is exactly
    // what Section 12's monitor exists to detect.
    isi_c = en_isi ? (atten_c + (prev_q >>> 2)) : atten_c;
 
    dirty_sample = en_noise ? (isi_c + noise_offset) : isi_c;
    dirty_valid  = clean_valid && !en_skip;
  end
 
endmodule

Classification: non-synthesizable, verification only.

What it teaches: how to build a stimulus model that states its own limits in the file, and how to make one mode of it structurally honest. The ISI mode biases toward the previous sample, which is the defining behaviour of channel memory — so a test using it genuinely exercises Section 12's correlation logic in the direction that logic is designed to detect. The attenuation and noise modes make no such claim and say so.

Deliberately simplified: everything physical. There is no channel here.

Production implication: models like this outlive their intended scope and get cited as evidence. The only reliable defence is a disclaimer in the source file, in the path of anyone reading the code — not in a document nobody opens.

16. Assertions

Every property below is a property of these teaching models. None is an IEEE 802.3 requirement — 802.3 specifies electrical characteristics measured at defined test points, and no assertion on RTL can express those.

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
// ─── Safety: the decision matches the thresholds ───────────────────────────
// Catches: an off-by-one in the threshold comparison loop, which shifts
// every decided symbol by one level. Presents as total data corruption on a
// link whose margin instrumentation reports perfect health.
property p_slicer_matches_thresholds;
  @(posedge clk) disable iff (!rst_n)
  (sym_valid && (LEVELS == 2)) |->
    (symbol == ($past(sample) > $past(threshold[0])));
endproperty
 
// ─── Causation: confidence reflects distance, not the decision ─────────────
// Catches: low_confidence derived from the symbol value rather than from the
// margin -- which produces a confidence signal that is a function of the
// data and therefore useless.
property p_confidence_tracks_margin;
  @(posedge clk) disable iff (!rst_n)
  sym_valid |-> (low_confidence == (margin < GUARD));
endproperty
 
// ─── Safety: margin is a distance and cannot be negative ───────────────────
// Catches: a signed/unsigned mix in the subtraction, which wraps a small
// distance to a huge one and silently reports excellent margin on a link
// that is about to fail.
property p_margin_is_a_distance;
  @(posedge clk) disable iff (!rst_n)
  sym_valid |-> (margin <= (1 << (SAMPLE_W-1)));
endproperty
 
// ─── Ordering: binning is against the PRECEDING pattern ────────────────────
// The property that protects the entire measurement of Section 12. Catches:
// history updated before the bin index is taken, which correlates each
// outcome against itself and produces a meaningless histogram that looks
// perfectly plausible.
property p_bin_uses_prior_history;
  @(posedge clk) disable iff (!rst_n)
  sym_valid |-> (bin_idx == $past(hist_q[$clog2(BINS)-1:0]));
endproperty
 
// ─── Conservation: every symbol lands in exactly one bin ───────────────────
// Catches: a binning path that can drop a sample, which biases the histogram
// in a way no downstream analysis can detect or correct.
property p_every_symbol_binned;
  @(posedge clk) disable iff (!rst_n)
  sym_valid |=> (bin_count[$past(bin_idx)] == $past(bin_count[$past(bin_idx)]) + 1);
endproperty
 
// ─── Safety: an event bin never exceeds its sample bin ─────────────────────
// Catches: counting an event without counting the sample, which produces an
// error rate above one and destroys trust in the whole measurement.
property p_events_bounded_by_samples;
  @(posedge clk) disable iff (!rst_n)
  (bin_events[0] <= bin_count[0]);
endproperty
 
// ─── Stability: the window minimum only falls within a window ──────────────
// Catches: a running minimum that is not reset when the window closes, so
// every subsequent window inherits the worst sample ever seen and the trend
// flattens into a useless constant.
property p_running_min_is_monotone_in_window;
  @(posedge clk) disable iff (!rst_n)
  (sym_valid && !$rose(window_valid)) |=> (run_min_q <= $past(run_min_q));
endproperty
 
// ─── Safety: the historical worst survives a clear ─────────────────────────
// Catches: worst_ever_margin folded into the `clear` branch, which lets an
// operator destroy the installation's history without knowing they did.
property p_worst_ever_survives_clear;
  @(posedge clk) disable iff (!rst_n)
  clear |=> (worst_ever_margin <= $past(worst_ever_margin));
endproperty
 
// ─── Conservation: burst length is consecutive, not cumulative ─────────────
// Catches: a burst counter that never resets on a clean symbol, turning the
// longest-burst metric into a total error count and erasing the distinction
// between a reflection and the noise floor.
property p_burst_resets_on_clean;
  @(posedge clk) disable iff (!rst_n)
  (sym_valid && !symbol_error) |=> (burst_q == 0);
endproperty
 
// ─── Bounded response: a window always closes ──────────────────────────────
// Catches: a window counter that can be starved, so window_valid never
// asserts and the trend has no data points at all.
property p_window_closes;
  @(posedge clk) disable iff (!rst_n)
  $rose(sym_valid) |-> ##[1:WINDOW+1] window_valid;
endproperty
 
// ─── Mutual exclusion on the memory verdict ────────────────────────────────
// Catches: memory_suspected asserted with no events recorded, which is a
// verdict formed from an empty sample.
property p_memory_verdict_needs_events;
  @(posedge clk) disable iff (!rst_n)
  memory_suspected |-> (bin_events[worst_bin] != 0);
endproperty
 
// ─── Safety: the scan never disturbs the data path ─────────────────────────
// The property that makes in-service scanning acceptable at all. Catches:
// an implementation that lets the offset sampler's decision reach the
// datapath, which would corrupt live traffic to take a measurement.
property p_scan_never_alters_decisions;
  @(posedge clk) disable iff (!rst_n)
  sym_valid |-> (symbol == ref_symbol);
endproperty
 
// ─── Conservation: the reported width is contiguous ────────────────────────
// Catches: a width computed as a TOTAL of passing offsets rather than as the
// widest contiguous run, which reports a wide eye from a non-monotonic
// interpolator's scattered passes.
property p_eye_width_is_contiguous;
  @(posedge clk) disable iff (!rst_n)
  scan_done |-> (eye_width_steps <= PHASE_STEPS);
endproperty
 
// ─── Bounded response: a scan terminates ───────────────────────────────────
// Catches: a dwell or phase counter that can stall, leaving scan_done low
// forever and a measurement that never reports.
property p_scan_terminates;
  @(posedge clk) disable iff (!rst_n)
  $rose(scan_start) |-> ##[1:(PHASE_STEPS*DWELL)+2] scan_done;
endproperty

17. Verification

Scenarios

  1. Clean samples, well away from the threshold. Verify correct symbols, low_confidence low, and margin large. The nominal case.
  2. A sample exactly on the threshold. The boundary. Verify the decision is deterministic — the same input always gives the same symbol — and that margin reads zero rather than wrapping.
  3. A sample one unit inside the guard band, and one unit outside. Two runs. Verify low_confidence asserts on the first and not the second, and that the boundary is where the parameter says.
  4. Thresholds changed while running. Verify the decision follows the new thresholds on the next sample and that margin is recomputed against them, not against a stale copy.
  5. PAM4 configuration. Reparameterise to four levels and verify all three thresholds are used, that each of the four symbol values is reachable, and that margin reports the distance to the nearest threshold rather than to a fixed one.
  6. Attenuation via the injector. Sweep atten_shift and verify margin falls monotonically while symbols stay correct — the eye closing without errors yet, which is precisely the condition the instrumentation exists to catch.
  7. Uncorrelated noise. Enable noise only, run long, and verify the memory monitor's bins stay flat and memory_suspected stays low. This is the negative control and it is as important as the positive one.
  8. Pattern-correlated ISI. Enable the ISI mode and verify the bins become peaked and memory_suspected asserts. Together with scenario 7 this proves the monitor discriminates rather than merely counting.
  9. Both at once. Verify the ISI signature is still detected under added noise, and record the noise level at which it stops being — that number is the monitor's sensitivity and it belongs in the documentation.
  10. Binning order. Drive a known symbol sequence and check by hand that each outcome landed in the bin of the preceding pattern. This is the scenario for p_bin_uses_prior_history, and getting it wrong produces a plausible-looking histogram that means nothing.
  11. Window boundary. Verify the running minimum resets when a window closes, and that a very low margin in window N does not depress window N plus one.
  12. Clear during operation. Verify the counters zero, and that worst_ever_margin does not.
  13. Burst against scattered errors. Inject five consecutive errors, then five errors separated by clean symbols. Verify longest_error_burst reads five in the first case and one in the second, with c_symbol_error reading five in both. The discrimination is the point.
  14. Counter saturation. Drive a bin to maximum and verify it holds, and that memory_suspected still behaves sensibly with a saturated bin.
  15. Reset mid-window. Verify no partial window is reported as valid.
  16. Sample skip. Enable en_skip and verify no symbol is produced, no bin advances, and the history does not shift — a dropped sample must not silently rotate the correlation.
  17. A clean phase scan. Run eye_phase_scanner with the two samplers agreeing across a contiguous middle range. Verify eye_width_steps equals that range and eye_centre_step lands in its middle.
  18. A non-monotonic interpolator. Drive disagreements so that passing offsets appear at both ends of the scan with failures between them. Verify the contiguity rule reports the widest contiguous run rather than the total count — a design without the rule reports a wide eye from nonsense.
  19. An off-centre sampling point. Make the passing run sit near one end. Verify eye_centre_step reports the offset, which is the finding: the link works with less margin than it should.

What the checker must own

  • A reference slicer in the testbench: an independent implementation of the threshold decision. Small, and it catches every comparison-boundary regression.
  • A binning scoreboard that recomputes the expected histogram from the driven sequence. It must implement the preceding-pattern rule independently, or it will replicate the design's bug.
  • Trend checking over windows, not per-transaction checks. Scenario 17 has no per-transaction failure at all; the finding exists only in the sequence of window minima.
  • Coverage crosses of margin band against low_confidence against symbol_error. The bin (large margin, low_confidence asserted) must be unreachable, and (small margin, no symbol_error) must be well populated — that second bin is the healthy-but-degrading state, and a run that never hits it has not exercised the instrumentation at all.

18. Debugging — Margin First, Then Signature

The symptom: a link that works but errors occasionally. No obvious cause, no correlation with anything anyone has noticed.

Step 1 — read the margin, not the error count. window_min_margin and its trend answer a question the error counter cannot: is this link comfortable or is it living on the edge? A link with plenty of margin that errors occasionally has an event problem. A link with margin near the guard band has a budget problem, and they are fixed differently.

Step 2 — read longest_error_burst. This partitions the event problem in one register read:

ReadingWhat it meansWhere to look
bursts of one, scatteredthe noise floor is occasionally crossing the thresholdthe budget: margin is too thin
bursts of a few, repeatingsomething discrete and periodica reflection, or an aggressor switching
long bursts, rarea gross eventsupply transient, mechanical disturbance, a lock loss

Step 3 — read the memory monitor. This is the measurement that names the physics:

  • Flat bins — the cause is not correlated with the data. It is external: interference, crosstalk from another channel, supply noise. Quiesce the neighbouring channels and re-measure; if the errors stop, you have the aggressor.
  • Peaked bins — the channel has memory. This is ISI, and no amount of shielding will help. The fix is equalisation, a shorter or better channel, or a lower rate.

Those two conclusions send two different teams in two different directions, and Step 3 is what chooses between them. Skipping it is why so much time gets spent shielding a channel whose problem was its own loss.

Step 4 — if the bins are peaked, use the reflection arithmetic. Section 5 gave the relation: an echo arrives delayed by twice the propagation time to the discontinuity, at roughly 174 ps per inch. If the dominant bin corresponds to a pattern two symbols back at 97 ps per symbol, that is about 194 ps of delay, which puts the discontinuity somewhere near half an inch away. That is a location, and it is derived from a register read.

Step 5 — only now attach an instrument. An eye measurement is the right tool, and Steps 1 through 4 tell you where to probe, what to look for, and what you expect to see. Attaching a scope first and then forming a theory is the expensive order.

The method stated once: margin says whether the link has room; burst length says whether the cause is continuous or discrete; the correlation histogram says whether it is the channel or the environment. Three register reads, and the answer determines who owns the problem.

19. Common Misconceptions

"Differential signalling cancels noise."

The wrong model: the pair is immune to interference.

What it costs: a link erroring at high rate gets investigated as an interference problem. Someone adds shielding, changes cable routing, chases a switching supply — and none of it helps, because the actual cause was the channel doing something to the signal itself.

The corrected model: it cancels the component of a disturbance common to both conductors, to the extent the path and receiver are balanced, and only while the common-mode voltage stays inside the receiver's input range. It does nothing about attenuation, inter-symbol interference or reflections — all of which are differential, because they are the signal itself arriving wrong.

"A trace shorter than the wavelength is just a wire."

The wrong model: transmission-line behaviour begins somewhere far away.

What it costs: impedance discontinuities get treated as cosmetic. A split reference plane, a layer change without a stitching via, a connector footprint with the wrong geometry — each creates a reflection, and none of them appears on a schematic.

The corrected model: compare propagation delay against the unit interval. At roughly 174 ps per inch and a 97 ps unit interval, a six-inch trace holds about ten symbols simultaneously. The two ends are not the same node in any meaningful sense, and every discontinuity along it reflects a computable fraction of the wave.

"Peak-to-peak jitter is a number."

The wrong model: jitter has a worst case you can measure and budget against.

What it costs: a measurement taken over a short run understates the tails badly, the budget closes on paper, and the link fails in the field at a rate nobody predicted — because the failing excursions only occur every few minutes and the bench run lasted seconds.

The corrected model: jitter splits into a bounded deterministic part and an unbounded Gaussian random part. Peak-to-peak random jitter grows with observation time and is meaningless without a probability attached, which is why it is quoted at a bit error rate: TJ(BER) = DJ + Q(BER)·RJ_rms, with Q about 14 for 1e-12. Section 7's arithmetic showed a 1.5 ps random term outweighing a 20 ps deterministic one after that multiplication.

"A closed eye means a broken link."

The wrong model: if you probe a link and the eye is closed, it cannot be working.

What it costs: you condemn a functioning design, or you spend a long time trying to open an eye at a point where it was never meant to be open.

The corrected model: the eye is a property of a point in the system, not of the link. It is wide at the transmitter, smaller at the receiver's package, and open again after the receiver's equaliser — which is the entire purpose of equalisation. At high rates a completely closed eye at the receiver pins with a working link is normal, not exceptional. Ask where the eye was measured before concluding anything.

"No errors means the link is healthy."

The wrong model: the error counter is the health metric.

What it costs: this is the failure mode of Scenario 17. A channel ages, margin falls for months, and the error counter reads exactly zero the entire time — right up until it crosses the threshold and the link fails abruptly, with no warning anyone could have acted on.

The corrected model: errors are a cliff; margin is a slope. window_min_margin and the low-confidence rate degrade gradually and give months of notice. A link with zero errors and margin that has halved since installation is failing, and only the margin instrument can see it.

20. Interview Reasoning

"Why does differential signalling help, and what does it not help with?"

The answer that ends the topic gives the decomposition — the receiver responds to the difference, so a disturbance common to both conductors moves entirely into the average and contributes nothing — and then immediately names the limits: it depends on balance, it fails outside the input range, and it does nothing about attenuation, ISI or reflections because those are differential. Naming the limits is what separates understanding from recital.

"How would you tell inter-symbol interference from noise on a running link?"

Correlation with the data pattern. ISI is caused by the preceding symbols, so binning errors by preceding pattern gives peaked bins; noise is uncorrelated and gives flat ones. A strong answer notes this is measurable from inside the chip with a few hundred gates, and that the two answers send different teams in different directions — equalisation and channel work for one, interference hunting for the other.

"A link has been up for a year with zero errors. Is it healthy?"

The expected answer is yes; the correct answer is that the question cannot be answered from an error count. Margin degrades gradually and errors appear as a cliff, so a link can be months into failing with a perfectly clean counter. The follow-up worth anticipating is what you would measure instead — the minimum margin over a window, trended against its value at installation.

21. Understanding Check

Because the receiver measures the difference between the conductors, and a disturbance that lands on both equally cancels exactly in a subtraction.

Formally: add the same n to both. Vdiff = (Vp + n) − (Vn + n) = Vp − Vn, unchanged. Vcm = (Vp + Vn)/2 + n, which absorbs all of it. The noise did not get smaller — it moved into the coordinate nobody is looking at. The twisting of Chapter 3.1 is what makes "equally" true.

Limit one — balance. The cancellation assumes the disturbance appears equally and that the receiver subtracts with equal weight. Trace-length mismatch, an asymmetric via, gain imbalance in the input stage — any of these converts a fraction of the common-mode disturbance into differential signal, which is indistinguishable from data, because differential is the receiver's definition of data. Common-mode rejection ratio quantifies this, it degrades with frequency, and it is a property of the whole path rather than of the receiver alone.

Limit two — range. Rejection is not immunity. Push the common-mode voltage outside the amplifier's input range and the input stage stops behaving linearly; at that point the subtraction has stopped applying at all. This is one of the reasons the transformer of Chapter 3.1 matters: it breaks the DC path that would otherwise let two equipment grounds impose an arbitrary offset.

The follow-up to be ready for: so what does differential signalling not help with? Attenuation, ISI and reflections — all differential, all the signal itself arriving wrong.

22. What's Next

The claim this chapter set out to establish: a PHY does not read bits, it infers symbols from a distorted waveform, and every mechanism in it protects one of two margins.

Differential signalling is the largest single deposit into that budget — it removes the dominant environmental noise source by a change of coordinates, before the receiver does any work. What remains is what the channel itself does: attenuate more at high frequencies, reflect at every impedance step, and smear each symbol into its neighbours. Those are deterministic, which is why they are correctable, and pattern-correlated, which is why they are distinguishable from noise in a few hundred gates.

The eye is the budget, on two axes. Jitter closes it horizontally, attenuation and noise vertically, and inter-symbol interference — uniquely — closes it both ways, from one cause.

Chapter 3.4 — Why the PHY Is Internally Layered now returns to the sublayer split Chapter 2.6 introduced and gives it the depth it needs. With this chapter's picture in place, the split becomes explicable rather than merely assertable: the PCS owns what is true of the bit stream regardless of the medium, the PMD owns what is true of the medium regardless of the coding, and the PMA owns the conversion between them — and it is exactly the analog boundary developed here that decides which responsibilities land on which side.

Beyond that, Chapter 3.5 owns the codes, and Chapter 3.6 asks what each additional signal level costs in the vertical margin this chapter measured.

The full path is on the Ethernet curriculum index.

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Standards & specifications

Governing standard
IEEE Std 802.3 (Ethernet)(opens IEEE in a new tab)

Defines the Ethernet MAC, the media-independent interfaces and the physical-layer sublayers, including framing, access control, auto-negotiation and per-rate PHY specifications. VLAN tagging, priority and time-sensitive shaping are defined by IEEE 802.1, not by 802.3.

This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.

Where this fits

Part of the Ethernet curriculum.