140Total chapters
26Modules
140Chapters live
26 / 26Active modules
Networks before frame fields
Why networking exists, shared-media limits, and packet switching come first — so the MAC/PHY split, frames, and switching land on a real mental model.
Interview-ready depth
A leveled interview module plus per-chapter interview weighting — MAC vs PHY, RGMII, VLANs, switching, PTP, DMA, and the misconceptions that trip candidates.
Design → verify → debug
MAC RTL (frame parser, CRC engine, DMA, FIFOs), a UVM Ethernet agent, and packet-capture debugging for CRC errors, link failures, and DMA issues.
Ethernet Complete Curriculum
Your Learning Roadmap
140 chapters · 26 modules — MAC/PHY, frames, switching, VLANs, PTP, TSN — networks down to RTL.
140of 140 chapters live
100% complete
Module 1
Why Ethernet Exists
Module 2
Ethernet System Architecture
Module 3
The Ethernet PHY
Module 4
The MAC/PHY Boundary
Module 5
The Ethernet Frame and Addressing
Module 6
CRC and the Frame Check Sequence
Module 7
The MAC Datapath
Module 8
Ethernet Timing and Performance
Module 9
Ethernet Speed Generations
9.110 Mbps — The Original Shared-Medium MAC9.2100 Mbps — Fast Ethernet and the Switch Transition9.31 Gigabit — Four Pairs, Echo Cancellation and GMII9.410 Gigabit — 64B/66B, XGMII and the End of Shared Media9.525G to 100G — Per-Lane Rate and Lane Aggregation9.6200G to 800G — PAM4, FEC and the Modern Data-Centre Link
Module 11
Link Bring-Up and Auto-Negotiation
Module 12
Ethernet Switching
Module 13
VLANs
Module 14
Flow Control
Module 15
Link Aggregation
Module 16
Precision Time Protocol
Module 17
Time-Sensitive Networking
Module 18
Ethernet in SoCs
Module 19
Ethernet RTL Design
Module 20
Ethernet Verification
Module 21
Ethernet Debugging
Module 22
Ethernet in Automotive
Module 23
Ethernet in Real Systems
Module 24
Ethernet against Other Interconnects
Module 25
Ethernet Misconceptions Engineers Have
Module 26
Design Review and Interview Readiness