Timing Windows

Chapter 20.3 §12 said a read should be sampled near the centre of the data rather than at its transitions, and deliberately gave no figures. 20.4 §16 said a write-levelling result should sit offset from the reported boundary, and did not say how far.

Both were incomplete on purpose, because both answers need the same thing:

The device publishes how much of a bit interval a receiver can rely on. It publishes it in unit intervals, and it publishes it twice — once for the device as a whole and once for a single pin — because those are different numbers.

This chapter reads those parameters, and it also documents something worth noticing: the published window is not the subtraction most people expect it to be, and understanding why is a useful lesson about datasheet parameters in general.

1. A Bit Is a Region, Not an Instant

The mental shift the chapter rests on.

A beat of data occupies an interval. Within that interval the signal is not uniformly usable: it is transitioning at the start, settled in the middle, and beginning to transition again at the end. A receiver samples at one instant, and where that instant falls inside the region decides whether the value it gets is the value that was sent.

  CONCEPTUAL — NOT TO SCALE.

     transition              transition
         |                       |
         v                       v
    -----+=======================+-----
         |<--- valid region ---->|
         |          ^            |
         |          |            |
         |    a sample here      |
         |    has margin on      |
         |    both sides         |

Two quantities therefore matter for any chosen sample point, and they are not the same quantity:

Setup margin — how long the data had been stable before the sample. A sample too close to the leading transition has little.

Hold margin — how long the data remains stable after the sample. A sample too close to the trailing transition has little.

2. What the Device Publishes

The figures. One device family, named, with parameter names attached.

Three readings, and the third is the one nobody expects.

The window narrows with rate. tDQSQ grows from 0.16 to 0.20 UI and tQH shrinks from 0.76 to 0.70 UI across the grades. Both move in the unhelpful direction, which is what the rate-scaling argument of 6.10 §1 predicts arriving as published numbers.

The per-pin window is wider than the per-device window. tDVWp exceeds tDVWd at every grade. §5 is about why, and the difference turns out to quantify something 20.2 could only describe.

And tQH − tDQSQ is not tDVWd. Compute it: at DDR4-3200 it is 0.70 − 0.20 = 0.50 UI, while the published tDVWd is 0.64 UI. The datasheet describes the data valid window as derived from tQH − tDQSQ per UI — and the published figure is nonetheless larger than the subtraction of the tabulated limits at every grade.

3. What Eats the Window

§2's figures are what the device contributes. A receiver does not get to spend all of it, and knowing what the other claimants are is the difference between a budget and a number.

Only the first three are in §2's table. The device publishes what the device is responsible for; the remaining six are contributed by the system the device is placed in, and none of them appears in any datasheet because none of them is the device vendor's to specify.

One consequence worth carrying into the next module. Because the real window is measured rather than derived, its width is a result, not an input — and a result that changes with the board, the part, and the day's temperature. That is the argument for periodic recalibration (19.5 §4) restated from the margin side: a setting chosen against yesterday's window is spending a budget that has since moved.

4. Where the Margin Goes

The two margins sum to the region, so they trade one for one. That is §1's insight as a picture, and it is why the published window matters more than either individual parameter: the window is what you have to divide, and tDQSQ and tQH describe the edges you are dividing between.

Now the same region with a badly placed sample:

Nothing about the device changed between those two figures. The region is the same width; the sample moved. The second configuration works — until temperature, voltage or a channel effect moves the trailing transition slightly earlier, at which point it does not.

That is what “margin” buys: tolerance to movement. A sample with margin on both sides survives conditions changing in either direction. A sample with margin on one side only survives changes in one direction, and the failure when it comes is conditional — which is 20.3 §12's varying corruption, now with a mechanism.

5. Per Device and Per Pin

The two window parameters differ, and the difference is a quantity Chapter 20.2 could only name.

tDVWp — per pin. The window available on one DQ pin, relative to its strobe. It excludes the variation between pins, because it describes a single pin.

tDVWd — per device. The window available across all the device's DQ pins simultaneously. A receiver using one sampling point for a whole lane must fit inside this one, because the point has to work for every pin at once.

  the difference, computed from §2's verified figures

  grade        tDVWp    tDVWd    difference
  ─────────    ─────    ─────    ──────────
  DDR4-1600     0.66     0.63       0.03
  DDR4-1866     0.66     0.63       0.03
  DDR4-2133     0.69     0.64       0.05
  DDR4-2400     0.72     0.64       0.08
  DDR4-2666     0.72     0.64       0.08
  DDR4-2933     0.72     0.64       0.08
  DDR4-3200     0.72     0.64       0.08

  all values in UI

That difference is the per-bit spread — how much the pins of one device disagree about where their valid region sits. And it grows with rate, from 0.03 UI at the slowest grade examined to 0.08 UI at the fastest.

6. The Write Side Has Its Own Window

Everything so far has been the read direction, because 20.2 §4 established that the read window is the one the PHY has to work at. The write direction has a window too, and it is specified differently — which is worth seeing, because the difference follows from who is receiving.

On a write the device is the receiver. So the parameters are input requirements the controller must satisfy, rather than output guarantees the controller can rely on. That inverts the grammar of every figure.

Three observations, and they are structurally different from §2's.

tDIPW is a requirement on pulse width, not a window to sample inside. It says each data pulse the controller drives must be at least 0.58 UI wide as the device sees it. That is a constraint on what the channel may do to the signal — a pulse arriving narrowed below it is unacceptable regardless of where the strobe sits. It is the write-side counterpart of a valid window, expressed from the receiver's side.

tDSS and tDSH are symmetric at 0.18 CK. Both the setup and the hold requirement on the DQS falling edge relative to CK rising are the same figure, which makes them a tolerance band: the falling edge must land within ±0.18 CK of CK's rising edge. That symmetry is not a coincidence — it is a band centred on a target, which is exactly what a levelling procedure aims at.

And tDQSS widens as the preamble lengthens. 0.27 CK with a one-cycle preamble, 0.50 CK with a two-cycle one. A longer preamble gives the device more strobe before the data arrives, and the tolerance on where that strobe starts widens with it.

What this means for the two remaining modules. The write side has a target (tDQSS), a symmetric tolerance (tDSS/tDSH), and a one-bit detector to find it (20.4 §3) — a well-posed search. The read side has a width (tDVW) with no published position and no detector at all. Those are different search problems, which is why Module 21 treats write levelling and read levelling as separate chapters rather than one procedure applied twice.

7. Generation Scope, Stated Explicitly

Every figure in §2 and §6 comes from one DDR4 device family. What transfers to other generations and what does not is worth separating, because the failure mode of getting this wrong is a budget that looks rigorous and is wrong by a large factor.

The structure transfers. A bit is a region; a sample divides it into setup and hold; the region narrows with rate; a single sampling point per lane is bounded by the intersection across pins. None of that is DDR4-specific — it follows from source-synchronous transfer (20.1) and from grouping (20.2).

The grammar transfers. Read parameters in UI against DQS, write parameters in CK against the clock, for §6's reason. An unfamiliar table can be read with that key.

The numbers do not transfer. tDQSQ of 0.20 UI at DDR4-3200 is that device family's specification at that grade. A different generation, vendor or density has its own table, and there is no scaling rule that converts one into another.

And some of the structure itself changes by generation. Chapter 19.2 §3 established that a DDR4 DIMM presents one 72-bit channel while a DDR5 DIMM presents two independent 32-bit subchannels — which changes how many lanes a controller manages per channel and therefore how many independent windows it must satisfy simultaneously.

The practical rule: carry the reasoning, look up the numbers. A budget built from the right structure and the wrong table fails in a way that looks like a hardware problem, and it is one of the more expensive ways to be wrong.

8. Early, Centred, Late

The comparison that makes the trade concrete, using the verified DDR4-3200 per-device window of 0.64 UI and treating the region as spanning that fraction of a bit interval.

  EDUCATIONAL — positions in UI, region width from §2's verified
  tDVWd for DDR4-3200. The region's PLACEMENT within the bit interval
  is illustrative; its WIDTH is the published figure.

  region: 0.18 UI .. 0.82 UI   (0.64 UI wide, centred for illustration)

  sample at    setup margin    hold margin    smaller of the two
  ─────────    ────────────    ───────────    ──────────────────
   0.25 UI        0.07            0.57              0.07   <- early
   0.50 UI        0.32            0.32              0.32   <- centred
   0.75 UI        0.57            0.07              0.07   <- late

The centred sample's worst-case margin is more than four times the other two. That is the arithmetic behind centring: it maximises the smaller margin, and the smaller margin is what fails first.

The early and late cases are symmetric in this model and asymmetric in reality. At 0.25 UI the setup side is thin; at 0.75 UI the hold side is. Which of those is more dangerous depends on which transition moves more under real conditions — and in a real channel they do not move equally. §1's callout flagged this, and it is why Module 22 can shift the optimum away from the geometric centre.

What this table cannot tell you is where the region actually sits within the bit interval on a given system. tDVWd gives its width; its position depends on the path, and finding it is exactly what read training measures (Module 21). A width without a position is half the information, which is why a datasheet alone does not let you set a sampling point.

9. The Window in Sequence

Four owners, one window. The datasheet publishes a width, the channel takes some of it, training finds where what is left actually sits and picks a point in it, and the capture hardware lives with that choice on every beat. This chapter owns only the first box — and the diagram exists so that the other three are visibly somebody else's.

10. Margin Over a Burst

EDUCATIONAL — the region and sample positions are in UI from §8; the cycle grid shows which beat is being sampled, not sub-interval position. A cycle grid cannot represent phase, and §4's figures carry that instead.

Watch the two margin rows move in opposite directions while their sum stays constant. That is §1's trade, happening without anybody changing a setting — the region moved, and a fixed sample point therefore sits differently inside it.

And watch what does not change. beat_valid stays high, the beat indices stay correct, the framing is right. Only data_trust drops — and data_trust is not a signal any real receiver has. It is drawn here to make visible the thing that is invisible in hardware, which is exactly 20.3 §12's point restated with a mechanism.

11. A Model for Classifying a Sample Point

// ─────────────────────────────────────────────────────────────────────
// capture_window_model
//
// CLASSIFICATION
//   SIMULATION-ONLY EDUCATIONAL TIMING MODEL. Not synthesisable
//   capture hardware, and not intended to be synthesised.
//
//   One responsibility: given a valid region and a chosen sample
//   point, expressed in abstract sub-interval units, classify the
//   point and report the two margins.
//
//   IT IS A CLASSIFIER, NOT A SAMPLER. It never touches DQ.
//
// WHAT IT DOES NOT MODEL
//   - NO ELECTRICAL BEHAVIOUR. No voltages, no slew, no jitter
//     distribution, no metastability, no aperture. A point classified
//     "inside" here would not necessarily resolve correctly in
//     silicon; real margin is statistical and this model is not.
//   - NO SAMPLING. It does not capture data. Chapter 20.3 §1 explains
//     why no portable RTL in this module samples anything.
//   - NO SEARCH. It classifies ONE point. Sweeping points to find a
//     good one is Module 21's work, and a loop here would absorb it.
//   - NO WINDOW DISCOVERY. region_start and region_end are INPUTS.
//     Where the region actually sits on a real system is measured
//     (§8), not computed.
//   - NO CHANNEL EFFECTS. Module 22 owns what narrows the region.
//
//   UNITS: all quantities are in UNITS PER BIT INTERVAL, scaled by
//   SCALE. With SCALE = 100 a value of 50 means 0.50 UI. These are
//   the caller's abstract units; §2's verified figures can be entered
//   in them, but the model itself knows nothing about any device.
// ─────────────────────────────────────────────────────────────────────
module capture_window_model #(
  parameter int SCALE = 100,
  parameter int Q_W   = $clog2(SCALE + 1)
) (
  // ── The valid region, in scaled sub-interval units.
  input  logic [Q_W-1:0] region_start,
  input  logic [Q_W-1:0] region_end,

  // ── The chosen sampling point.
  input  logic [Q_W-1:0] sample_point,

  // ── Classification. Exactly one of these is high for a well-formed
  //    region, which §13's P1 asserts.
  output logic           before_region,
  output logic           inside_region,
  output logic           after_region,

  // ── The two margins of §1. Zero when the point is outside, because
  //    a negative margin is not a small margin -- it is a different
  //    condition, and reporting it as a number invites arithmetic on
  //    a quantity that has no meaning.
  output logic [Q_W-1:0] setup_margin,
  output logic [Q_W-1:0] hold_margin,

  // ── The smaller of the two: what actually fails first (§8).
  output logic [Q_W-1:0] worst_margin,

  // ── A region whose end is not after its start is malformed. Not a
  //    narrow window -- a nonsensical one.
  output logic           err_region_malformed
);

  if (SCALE < 2) $fatal(1, "capture_window_model: SCALE must be >= 2");

  assign err_region_malformed = (region_end <= region_start);

  assign before_region = !err_region_malformed && (sample_point <  region_start);
  assign after_region  = !err_region_malformed && (sample_point >  region_end);
  assign inside_region = !err_region_malformed
                      && (sample_point >= region_start)
                      && (sample_point <= region_end);

  // ── Margins, computed only when the point is inside. Guarding the
  //    subtraction rather than clamping afterwards: an unguarded
  //    subtraction on an outside point wraps to a large positive
  //    value, which would read as excellent margin.
  assign setup_margin = inside_region ? (sample_point - region_start) : '0;
  assign hold_margin  = inside_region ? (region_end   - sample_point) : '0;

  assign worst_margin = (setup_margin < hold_margin) ? setup_margin
                                                     : hold_margin;

endmodule

Simulating it. Enter §8's figures with SCALE = 100: region_start = 18, region_end = 82, and sweep sample_point. At 25 the model reports inside with a worst margin of 7; at 50, inside with 32; at 75, inside with 7 again. The worst-margin output traces out a triangle peaking at the centre, which is §1's trade as a curve — and reading that curve is the whole reason Module 21's searches look for a maximum.

Synthesis. It should not be synthesised, and that is the point of the classification header. Two comparators and two subtractors would synthesise perfectly well and would be actively misleading in a design — a block that reports margin implies margin is observable in hardware, and it is not. Chapter 20.3 §3 established that the capture contract carries no quality indication precisely because the hardware cannot produce one.

What is unrealistic about it — and the list is long enough to matter. The region has hard edges; a real one degrades gradually. The classification is binary; real marginal sampling has a failure probability. The model is static; real margins move continuously with temperature and voltage. And a point classified inside could still fail in silicon, because nothing here represents the receiver's own aperture. The model teaches the geometry of the trade and nothing about the physics, which is the most it can honestly do.

12. What the Assertions Prove

capture_window_model is combinational and has no clock, so these belong in a testbench or a bind unit sampled on the environment's clock, as Chapter 16.2 §10 established.

// ── P1. The classification is a partition: exactly one of the three
//    outcomes for any well-formed region. Catches boundary conditions
//    where a point at region_start or region_end falls through every
//    branch, or satisfies two.
property p_classification_is_partition;
  @(posedge clk) disable iff (!rst_n)
    !err_region_malformed
      |-> ($countones({before_region, inside_region, after_region}) == 1);
endproperty
a_classification_is_partition: assert property (p_classification_is_partition);

// ── P2. The margins sum to the region width whenever the point is
//    inside. THE property of §1: the two margins trade against each
//    other and their total is fixed. A model where they did not sum
//    would teach that margin can be created by moving the point.
property p_margins_sum_to_region;
  @(posedge clk) disable iff (!rst_n)
    inside_region
      |-> ((setup_margin + hold_margin) == (region_end - region_start));
endproperty
a_margins_sum_to_region: assert property (p_margins_sum_to_region);

// ── P3. Outside the region both margins read zero, never a wrapped
//    value. An unguarded subtraction would report an enormous margin
//    for the worst possible sample point.
property p_outside_reports_zero;
  @(posedge clk) disable iff (!rst_n)
    (before_region || after_region || err_region_malformed)
      |-> (setup_margin == '0 && hold_margin == '0 && worst_margin == '0);
endproperty
a_outside_reports_zero: assert property (p_outside_reports_zero);

// ── P4. worst_margin is genuinely the minimum. It is the quantity
//    that fails first (§8), so a model that reported the wrong one
//    would rank sample points wrongly.
property p_worst_is_minimum;
  @(posedge clk) disable iff (!rst_n)
    (worst_margin <= setup_margin) && (worst_margin <= hold_margin);
endproperty
a_worst_is_minimum: assert property (p_worst_is_minimum);

// ── P5. The centre maximises the worst margin. §8's arithmetic as a
//    property -- and the reason centring is the default rather than a
//    preference. Stated for the exact centre to avoid rounding.
property p_centre_maximises_worst;
  @(posedge clk) disable iff (!rst_n)
    (inside_region
     && (sample_point == (region_start + (region_end - region_start)/2))
     && (((region_end - region_start) % 2) == 0))
      |-> (worst_margin == ((region_end - region_start)/2));
endproperty
a_centre_maximises_worst: assert property (p_centre_maximises_worst);

// ── Covers. The boundary and outside cases are what a sweep through
//    the middle never reaches.
c_at_region_start: cover property (@(posedge clk) disable iff (!rst_n)
                     inside_region && sample_point == region_start);
c_at_region_end:   cover property (@(posedge clk) disable iff (!rst_n)
                     inside_region && sample_point == region_end);
c_before:          cover property (@(posedge clk) disable iff (!rst_n) before_region);
c_after:           cover property (@(posedge clk) disable iff (!rst_n) after_region);
c_malformed:       cover property (@(posedge clk) disable iff (!rst_n) err_region_malformed);

What they prove. That the classifier partitions correctly, that the margins trade rather than accumulate, that an outside point cannot masquerade as a good one, and that the centre maximises the worst margin — which is §8's conclusion made checkable rather than asserted.

What they cannot prove — and here the gap is the widest in the module. Nothing above establishes that a point classified inside_region would actually capture correctly in silicon. The model has no representation of aperture, jitter, slew, or the statistical nature of marginal sampling. A point one unit inside the region is classified identically to one at the centre, and in hardware those are entirely different propositions.

More fundamentally: the inputs are the claim. region_start and region_end are supplied, and the model adds nothing to their credibility. A region entered too wide produces confident margins that do not exist. Establishing the region is measurement — Module 21's — and no property over this model can substitute for it.

Vacuity. P5's antecedent requires an exactly-centred point and an even region width, which a random sweep essentially never produces; it needs directed stimulus. P2 and P3 are the load-bearing properties and both have reachable antecedents, but c_before, c_after and c_malformed are what establish that the outside and malformed paths were visited at all — a sweep confined to the interior exercises none of them.

13. Corner Cases

The odd-width row is worth a note because it is a real property of discrete settings rather than a modelling artefact. A region of odd width has no exact centre in integer units, so the two margins differ by one unit whichever way the point is placed. Chapter 20.4 §6 made the same observation about delay-control resolution: the optimum is a point and the settings are a lattice, and the gap between them is a real, if small, loss that Module 21 has to live with.

14. DV — Sweep It and Check the Shape

The independent model should not re-implement the comparisons; it should check the shape of the result, because the shape is the claim.

Build the reference as a table — for a fixed region, the expected (classification, setup, hold, worst) for every sample point from 0 to SCALE, generated arithmetically in the testbench. Then sweep the DUT across the same range and compare all four outputs at every point.

Then check three whole-sweep properties the RTL never states:

The worst-margin curve is unimodal. It rises to the centre and falls, with exactly one maximum. A model with a boundary error produces a notch or a plateau.

The sum is invariant inside the region. setup + hold must be constant across every interior point — P2 checks it pointwise, but a sweep makes a violation obvious as a step.

The classification changes exactly twice across the full sweep: once entering the region, once leaving. More transitions means a boundary is being evaluated inconsistently.

  WINDOW MODEL SWEEP MISMATCH
    SCALE = 100, region_start = 18, region_end = 82  (width 64)

    sample   expected                  observed
    ──────   ───────────────────────   ───────────────────────
      17     before, 0, 0, 0           before, 0, 0, 0          ok
      18     inside, 0, 64, 0          before, 0, 0, 0          <-- MISMATCH
      19     inside, 1, 63, 1          inside, 1, 63, 1         ok
      ...
      82     inside, 64, 0, 0          after,  0, 0, 0          <-- MISMATCH
      83     after,  0, 0, 0           after,  0, 0, 0          ok

    classification transitions observed : 2 (expected 2)
    sum invariant inside                : holds where inside
    worst-margin curve                  : unimodal, peak at 50 = 32

    diagnosis : both region boundaries are EXCLUSIVE in the DUT and
                inclusive in the reference. The comparisons use
                strict inequality where they should use >= and <=.
    why it matters : the two lost points are exactly the zero-margin
                boundaries -- the positions a training sweep uses to
                LOCATE the region's edges. Losing them makes the
                measured region two units narrower than it is, at
                every rate, silently.
    caught by : P1 does NOT fire -- the classification is still a
                valid partition, just a different one. Only the
                sweep comparison catches it.

The last line is why the sweep exists. An exclusive-versus-inclusive boundary error produces a perfectly self-consistent classifier that partitions correctly and satisfies every pointwise property. Only comparing against an independently generated expectation across the whole range finds it — and the points it loses are precisely the ones that matter to whoever is measuring the region.

Directed cases worth running: both boundaries exactly; one unit outside each; a malformed region in both forms; SCALE = 2; an odd-width region, confirming the one-unit asymmetry; and a region spanning the entire interval.

15. Debugging

Symptom: data errors that worsen with temperature, at a fixed setting. §10. The region drifted and the sample point did not. Check which margin is short — if the failure appears as temperature rises and the hold side was already the smaller, that is consistent. The fix is a better-centred setting or periodic recalibration (19.5 §4), not a different capture design.

Symptom: a timing budget rejects a design that works in hardware. Check whether the budget subtracted tQH − tDQSQ instead of using tDVW. §2's callout — that subtraction is over-pessimistic by design, and at DDR4-3200 it understates the window by 0.14 UI.

Symptom: one DQ bit in a lane is marginal and the others are fine. §5. The per-device window is the intersection of the per-pin windows, and a single sampling point sits inside the intersection. A bit whose own window is offset from the others is the one that runs out first. This is a per-bit deskew question (21.4), not a lane-level one.

Symptom: errors appear at the highest grade only. §2's first reading — tDQSQ grows and tQH shrinks with rate, so the window genuinely narrows. A setting with adequate margin at a lower grade may have none at the top one, and the same design is not marginal at both.

Symptom: the measured window is narrower than the datasheet's. Expected. The published figure is the device's contribution; the channel subtracts from it (Module 22), so a measured region is always at most the published one. A measured region wider than published is the surprising result and usually means the measurement is not finding the true edges.

Symptom: training converges on a setting near one edge of the region. Not necessarily wrong — §1's qualification allows an offset optimum when the two edges are threatened differently. But it is worth confirming that the asymmetry is real rather than an artefact of how the edges were detected, because a boundary-detection error looks exactly like a genuinely asymmetric channel.

16. Misconceptions

“Setup and hold are just datasheet numbers.” §1 — they are the two halves of a region a sample point divides, and they trade one for one. Consequence: the trade goes unnoticed and a sample point is chosen without reference to what it costs on the other side. Clue: a design discussion about margin that names only one of them.

“The valid window is tQH − tDQSQ.” §2's callout — the published window is larger, because subtracting two independent worst cases produces a case that need not occur. Clue: a hand-computed window that disagrees with the datasheet's own parameter.

“Moving the sample point improves margin.” It redistributes it. The region is fixed. Clue: an expectation that a phase adjustment can create margin that was not there.

“The centre is always optimal.” It maximises the smaller margin, which is the right default — but if one edge is degraded more than the other, the optimum is offset. Clue: a centring result defended without reference to channel asymmetry.

“One sampling point can use the per-pin window.” §5 — a single point must fit every pin, so it is constrained by tDVWd. Reaching tDVWp requires per-bit adjustment. Clue: a margin calculation using the per-pin figure for a lane-level setting.

“Per-bit skew is negligible.” §5's table — 0.08 UI at DDR4-3200, which is an eighth of the available window. Clue: a design that dismisses deskew without computing what it would recover.

“A simplified valid-window sketch is an eye diagram.” An eye diagram is a measurement showing accumulated real transitions with their statistical spread. §1's and §4's figures are geometric sketches with hard edges. They show the trade; they show nothing about probability. Clue: a conceptual sketch presented as measured margin.

“A digital assertion can prove the eye is open.” §12 — the model has no representation of aperture or jitter, and a point one unit inside the region classifies identically to a centred one. Clue: margin sign-off from simulation.

“These figures apply to all DDR.” §2 states the scope: one device family, one generation, named grades. Clue: a DDR5 budget built from DDR4 numbers.

17. Interview Reasoning

“What is setup margin and what is hold margin?” The stable time before and after the sampling instant. The strong answer continues: they sum to the valid region, so moving the point trades one for the other.

“Why is centring the usual goal?” It maximises the smaller of the two margins, and the smaller one fails first. Then the qualification: not automatically optimal if the two edges are threatened unequally.

“How would you find the usable read window for a device?” Read the published data-valid-window parameter — not by subtracting the skew and hold limits, and being able to say why is the discriminating part.

“Why does a datasheet publish both per-device and per-pin windows?” Because a single sampling point must satisfy every pin, so it is bounded by the intersection. The difference quantifies per-bit skew and is what per-bit deskew recovers.

“Data errors worsen with temperature at a fixed setting. What moved?” The region, not the setting. Then which margin was short, and whether the answer is a better centre or periodic recalibration.

“Is a valid-window sketch an eye diagram?” No — one is geometry with hard edges, the other is a measurement with a statistical distribution. Knowing what the eye adds is the answer.

“What can simulation tell you about capture margin?” The geometry of the trade and the consistency of a budget. Not whether a given point resolves correctly, because aperture and jitter are absent from any RTL model.

18. Exercises

1. From §2's table, compute tQH − tDQSQ for DDR4-2400 and compare it with the published tDVWd. State which you would use in a budget and why.

2. Using the DDR4-3200 per-device window of 0.64 UI and a region from 0.18 to 0.82 UI, compute both margins for sample points at 0.30, 0.50 and 0.70 UI. Which point has the largest worst-case margin?

3. §5's table shows the per-bit spread growing from 0.03 to 0.08 UI. Express the DDR4-3200 spread as a percentage of the per-device window, and say what a per-bit deskew scheme would recover.

4. A region has an odd width in discrete units. Show that no setting gives equal margins, and give the best achievable worst-case margin.

5. Remove the inside_region guard from setup_margin. Compute what the model reports for a point one unit before the region, and say why that value is dangerous rather than merely wrong.

6. All five properties in §12 pass on a model whose boundaries are exclusive rather than inclusive. Describe what a training sweep using it would conclude about the region's width, and name the check that catches it.

7. Explain why capture_window_model is marked simulation-only, in terms of what a synthesised version would imply about the hardware.

8. §2's figures are one device family's. List three things you would need to know before applying them to a different system.

19. Module 20, Complete

Five chapters, one region.

A strobe converts absolute arrival into a relative budget. Chapter 20.1 reframed 6.10's conclusion: source-synchronous transfer does not remove uncertainty, it changes the variable — and it showed with an executable budget that the residual still consumes a third of an interval and that the cliff moves rather than disappearing.

The strobe's authority is per lane, and its phase differs by direction. 20.2 argued the byte-lane grouping from the physics rather than from convention, and established the asymmetry everything else rests on: a read strobe arrives aligned to the data's transitions, a write strobe arrives centred.

Capture is three stages and only one is RTL. 20.3 opened Module 19's box and found a shift, a sample, and a digital path — building the third, being explicit that the first two are technology-specific, and showing a burst with a perfect beat count and corrupt data that no property in the chapter can detect. It also established that an arriving burst cannot be told to wait, and derived the buffering that forces.

The write direction has a second, independent requirement. 20.4 showed that fly-by routing makes the strobe-to-CK relationship different at every device, that the controller can neither compute nor directly measure it, and that the device answers a one-bit question — leaving the search to Module 21.

And the region is published. This chapter supplied the figures, in unit intervals, from a named device: the window narrows with rate, the per-pin window exceeds the per-device one by an amount that quantifies per-bit skew, and the published window is deliberately not the subtraction of the individual limits.

The discipline every chapter repeated: the digital half is verifiable and the physical half is not. 20.3 §12 is the concrete form — every observable correct, the data wrong, no assertion firing. That is not a shortcoming of the verification; it is the boundary of what verification reaches, and it is why the next two modules exist.

Module 21 owns every search that spends this budget: where the region actually sits, which setting sits best inside it, and how per-bit adjustment recovers §5's difference. Module 22 owns why the region is narrower in a real system than in any datasheet.