DDR — Tutorials · VLSI Mentor

201Total chapters

34Modules

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Memory hierarchy first

Why SRAM is not enough, why DRAM exists, the memory wall, and the 1T1C-cell physics that produces every later DDR concept — the foundations the rest of the curriculum rides on.

Interview-ready depth

A dedicated interview module plus per-chapter interview weighting — tRCD, CAS latency, row-buffer hits / misses, controller scheduling, write leveling, performance tuning, silicon-bring-up debug.

Design → verify → debug

DDR controller (scheduler, queues, refresh) and PHY (training, DQS, calibration) RTL discipline, JEDEC-compliance verification, and trace-driven silicon debug — the full engineering loop.

DDR Complete Curriculum

Your Learning Roadmap

201 chapters · 34 modules — DRAM cell physics, controllers, PHY training, and DDR4 / DDR5 / LPDDR / HBM.

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Module 1

Why DRAM Exists

1.1The Memory Hierarchy 1.2Registers 1.3SRAM 1.4DRAM 1.5Flash 1.6Cost vs Density 1.7Why DRAM Dominates Main Memory 1.8The Memory Wall Problem

Module 2

DRAM Fundamentals

2.1Capacitor Storage 2.2Charge Storage and Leakage 2.3The Refresh Requirement 2.4The DRAM Cell (1T1C)2.5The Destructive-Read Property 2.6Restore Operations

Module 3

DRAM Array Architecture

3.1Rows 3.2Columns 3.3Bitlines 3.4Wordlines 3.5Sense Amplifiers 3.6Memory Matrices and Hierarchy

Module 4

DDR Evolution

4.1SDR SDRAM 4.2DDR (DDR1)4.3DDR2 4.4DDR3 4.5DDR4 4.6DDR5 4.7LPDDR Evolution 4.8HBM Overview

Module 5

DDR Architecture Overview

5.1The DDR Device Structure 5.2Banks 5.3Bank Groups 5.4Ranks 5.5Channels 5.6DIMMs 5.7The Memory-Subsystem View

Module 6

DDR Signals

6.1CK / CK# — The Differential Clock 6.2CKE — Clock Enable 6.3CS# — Chip Select 6.4RAS# — Row Address Strobe 6.5CAS# — Column Address Strobe 6.6WE# — Write Enable 6.7ODT — On-Die Termination Control 6.8RESET# — Asynchronous Reset 6.9DQ — The Data Bus 6.10DQS — The Data Strobe 6.11DM — The Data Mask 6.12Other Sideband Signals

Module 7

DDR Commands

7.1Activate (ACT)7.2Read (RD / RDA)7.3Write (WR / WRA)7.4Precharge (PRE / PREA)7.5Refresh (REF)7.6Mode-Register Set (MRS)7.7ZQ Calibration (ZQCS / ZQCL)

Module 8

DDR Addressing

8.1Row Address 8.2Column Address 8.3Bank Address 8.4Bank-Group Address 8.5Rank Selection 8.6Physical Mapping

Module 9

Activate and Precharge

9.1Row Opening 9.2The Row Buffer 9.3Row Hits 9.4Row Misses 9.5Row Conflicts 9.6Performance Impact

Module 10

Read Operations

10.1The Read Command 10.2CAS Latency (CL)10.3Data Return 10.4Burst Reads 10.5Read Timing Analysis

Module 11

Write Operations

11.1The Write Command 11.2Write Latency (CWL)11.3Burst Writes 11.4Write Recovery (tWR)11.5Write Timing Analysis

Module 12

Burst Operations

12.1Burst Length 12.2Sequential Burst 12.3Interleaved Burst 12.4Data-Transfer Efficiency

Module 13

DDR Timing Fundamentals

13.1Why Timing Parameters Exist 13.2Device Physics Behind Timing 13.3Timing Constraints Catalogue 13.4Command Scheduling

Module 14

Key DDR Timing Parameters

14.1tRCD — RAS-to-CAS Delay 14.2tRP — Row Precharge Time 14.3tRAS — Row Active Time 14.4tRC — Row Cycle Time 14.5tWR — Write Recovery 14.6tCCD — CAS-to-CAS Delay 14.7tRRD — Row-to-Row Delay 14.8tFAW — Four-Activate Window 14.9CL — CAS Latency 14.10CWL — CAS Write Latency

Module 15

Refresh Operations

15.1Why Refresh Exists 15.2Refresh Commands 15.3Refresh Scheduling 15.4Retention Time 15.5Refresh Bandwidth Impact

Module 16

Banks and Bank Groups

16.1Bank-Level Parallelism 16.2Bank-Aware Scheduling 16.3Performance Optimisation 16.4DDR4 / DDR5 Bank-Group Concepts

Module 17

DDR Controller Architecture

17.1The Command Scheduler 17.2The Command Queue 17.3The Refresh Manager 17.4Arbitration 17.5Request Handling

Module 18

Address Mapping

18.1Row-Bank-Column Mapping 18.2Mapping for Performance 18.3Spatial Locality 18.4Real-System Examples

Module 19

DDR PHY Fundamentals

19.1PHY Responsibilities 19.2Serialisation 19.3Timing Alignment 19.4DQS Handling 19.5PHY Calibration

Module 20

DQS and Data Capture

20.1Source-Synchronous Interfaces 20.2The DQS Concept 20.3Read Capture 20.4Write Leveling 20.5Timing Windows

Module 21

DDR Training

21.1Write Leveling Algorithm 21.2Read Leveling 21.3Gate Training 21.4Eye Centering 21.5Training Algorithms

Module 22

ODT and Signal Integrity

22.1On-Die Termination 22.2Reflections 22.3Signal Integrity 22.4High-Speed Effects

Module 23

DDR Performance

23.1DDR Latency Anatomy 23.2DDR Bandwidth 23.3Row-Buffer Locality 23.4Scheduling Optimisation 23.5Controller Policies

Module 24

LPDDR Fundamentals

24.1Mobile-Memory Mission 24.2Low-Power Features 24.3LPDDR4 Architecture 24.4LPDDR5 Architecture 24.5Mobile-Power Management

Module 25

DDR5 Architecture

25.1DDR5 Bank-Group Enhancements 25.2Dual Sub-Channels 25.3On-DIMM PMIC 25.4DDR5 New Capabilities

Module 26

HBM Fundamentals

26.1Why HBM Exists 26.22.5D Packaging for HBM 26.3Through-Silicon Vias (TSVs)26.4HBM for AI Accelerators

Module 27

DDR Verification

27.1JEDEC Compliance 27.2DDR Assertions 27.3DDR Monitors 27.4DDR Scoreboards 27.5DDR Functional Coverage 27.6DDR VIP Usage 27.7UVM Architecture for DDR

Module 28

DDR Debugging

28.1Training Failures 28.2Timing Violations 28.3Refresh Issues 28.4Calibration Failures 28.5Data Corruption 28.6Signal-Integrity Problems 28.7DDR Silicon Bring-Up

Module 29

DDR in SoC Architecture

29.1AXI-to-DDR Flow 29.2Memory Controllers in SoCs 29.3CPU Access Patterns 29.4DMA Access Patterns 29.5Accelerator Access Patterns

Module 30

DDR Interview Mastery

30.1Why DRAM Refresh?30.2Row-Buffer Question 30.3tRCD Question 30.4CAS-Latency Question 30.5Controller-Scheduling Question 30.6Training Question 30.7PHY Question 30.8Senior Performance Tuning 30.9Senior Verification Strategy 30.10Senior Silicon Debug

Module 31

DDR vs Other Memories

31.1DDR vs SRAM 31.2DDR vs LPDDR 31.3DDR vs HBM 31.4DDR vs GDDR

Module 32

Real Industry Case Studies

32.1CPU Memory Controllers 32.2Mobile SoCs 32.3GPUs 32.4AI Accelerators 32.5Data-Centre Servers

Module 33

DDR Design-Review Checklist

33.1Architecture Review Checklist 33.2RTL Review Checklist 33.3PHY Review Checklist 33.4Verification Review Checklist 33.5Performance Review Checklist 33.6Bring-Up Review Checklist 33.7Debug Review Checklist 33.8Interview Review Checklist

Module 34

DDR Misconceptions Engineers Have

34.1“CAS Latency Equals Memory Latency”34.2“Refresh Only Affects Idle Systems”34.3“DDR Bandwidth Equals Application Bandwidth”34.4“DDR Controller Is Simple Arbitration”34.5“Training Happens Only Once”34.6“DDR5 Is Just Faster DDR4”