AMBA AXI · Module 4

Write Transaction Waveforms

Annotated end-to-end AXI write waveforms — single-beat, burst, and stalled — assembling AW, W (WSTRB/WLAST), and B (BRESP) into one readable picture.

This chapter assembles everything in Module 4 into the picture you'll actually face on a logic analyzer or simulator: the end-to-end write waveform. We walk three canonical shapes — a single-beat write, a burst write, and a stalled write (backpressure on the data phase) — annotating each handshake so you can read AW, W (WSTRB/WLAST), and B (BRESP) at a glance. Then we distill a repeatable method for reading any write waveform. This is the Critical capstone of the write path: master these three pictures and you can debug a write on sight.

1. The Whole Write, Assembled

A write is three handshakes in sequence: AW launches it (address + shape), W delivers the data beats (WDATA/WSTRB, ending in WLAST), and B confirms it (BRESP). On a waveform you read it by finding those three transfer events — AWVALID && AWREADY, each WVALID && WREADY (with WLAST on the last), and BVALID && BREADY — and checking they agree: the W-beat count matches AWLEN+1, and the BRESP says it landed. The three shapes below are the same transaction under different conditions.

2. The Single-Beat Write

The simplest case: one address, one data beat, one response.

valid / ready (per channel)

Single-beat write — AW → W (WLAST) → B

12 cycles

AWLEN=0 (one beat); WLAST asserts on that single W beat; BRESP=OKAY on B completes the write.

Figure 1 — a single-beat AXI write. The address transfers on the AW handshake; the one data beat transfers on the W handshake with WLAST=1 (single beat); then the subordinate returns BRESP=OKAY on the B handshake. The write completes only when B is accepted. Three handshakes, AWLEN=0, one beat.

This is the baseline every other write is built from. AWLEN=0, so the single W beat carries WLAST=1, and the lone BRESP closes it. Note again that the data going out (the W handshake) does not finish the write — only accepting B does.

3. The Burst Write

Now one address launches multiple data beats. AW is accepted once; the W channel then streams AWLEN+1 beats, asserting WLAST on the last; finally one B response covers the whole burst.

Burst write — one AW, four W beats, one B

10 cycles

Figure 2 — a 4-beat burst write (AWLEN=3) end to end. AW is accepted at cycle 2 (address 0x20, 4-beat burst). The W channel delivers D0–D3 on cycles 2–5, with WLAST on D3 (cycle 5). After the data is accepted, the subordinate drives BVALID with BRESP=OKAY, accepted at cycle 8 — one response for the whole burst. The W-beat count (4) equals AWLEN+1.

Read it as the three phases: AW (cycle 2), the W burst (cycles 2–5, four beats, WLAST on the fourth), then B (cycle 8). The single BRESP covers all four beats — there is no per-beat write response. The gap between WLAST (cycle 5) and B (cycle 7–8) is the subordinate's processing latency, which is legal and unbounded (4.5).

4. The Stalled Write — Backpressure on the Data Phase

Real subordinates aren't always ready. Here the subordinate backpressures the W channel mid-burst by dropping WREADY; the manager holds WVALID and the data stable (stability rule) until it rises again.

Stalled write — backpressure on W

11 cycles

Figure 3 — a stalled burst write. After AW is accepted, the subordinate drops WREADY for cycles 4–5 (backpressure); the manager holds WVALID and D1 stable across the stall, and D1 transfers only when WREADY returns at cycle 6. The remaining beats follow, WLAST closes the burst, and B=OKAY completes it. The stall inserts bubbles but loses nothing.

The tell of a healthy stall: WVALID stays high and WDATA is unchanged (here D1 held) across the low-WREADY window, and the beat transfers the moment WREADY returns. Nothing is lost — the bubbles just lower throughput. Contrast with the dropped-VALID bug (3.6), where WVALID would illegally fall during the stall.

5. How to Read Any Write Waveform

The three shapes share one reading method — a repeatable sequence that turns a wall of signals into a verdict:

Figure 4 — the write-waveform reading method. Find the AW handshake (get the shape), count the W beats to WLAST (must equal AWLEN+1), check WSTRB on each beat (which bytes), then read B (BRESP for success, BID for pairing). Each step checks one channel against what AW declared.

In words: AW gives the contract; W and B are checked against it. Get AWLEN from AW, count W beats to WLAST (they must match), confirm WSTRB selects the intended bytes, then read BRESP for the verdict and BID to pair it. Every write bug from Module 4 shows up as a step that disagrees — wrong beat count, mis-placed WLAST, ignored/wrong WSTRB, a non-OKAY BRESP, or a mismatched BID.

6. Common Misconceptions

Myths to unlearn

"The write is done when WLAST goes out." No — it's done when B is accepted (BVALID && BREADY). The W phase ending just lets B begin.
"A burst gets a response per beat." A write gets one BRESP for the whole burst, regardless of beat count. (Per-beat status is the read channel's RRESP.)
"A gap between WLAST and B means something's wrong." That gap is the subordinate's processing latency — legal and unbounded. Only B before WLAST, or B never arriving, is a bug.
"During a stall the manager can change the data." No — WVALID and the held WDATA/WSTRB must stay stable across the low-WREADY window. Changing them is the mutated-payload bug.
"You read a write waveform left to right cycle by cycle." You read it by handshake events (AW, each W, B) and check them against AWLEN/WSTRB/BRESP — not cycle by cycle. The events are the structure.

7. Debugging Insight

🔍 Debugging insight — the four-step read localizes any write bug

Apply the method from §5 and each failure mode falls out at a specific step:

AW handshake missing or malformed? The master never issued the write, or AWSIZE > bus width / illegal WRAP length — the write is broken before any data. (Fix at the source.)
W beat count ≠ AWLEN+1, or WLAST mis-placed? Length mismatch — too few/many beats, or WLAST early/late. The subordinate (waiting for WLAST) may hang or take the wrong length (4.4).
Data wrong but counts fine? Inspect WSTRB — ignored strobes corrupt neighboring bytes; wrong strobes write the wrong lanes (4.2). Also check the stall windows: did WVALID/WDATA stay stable (no dropped-VALID/mutated-payload)?
B reports SLVERR/DECERR, or never comes? DECERR → address/map; SLVERR → inside the target (4.5); no B after WLAST → subordinate stuck or master not draining BREADY.

So a write waveform is never overwhelming: walk AW → W(+WSTRB) → B, and the failing step is the bug class. This is the single most useful waveform-reading skill for the write path.

8. Verification Insight

✅ Verification insight — these three shapes are your minimum write coverage

The single, burst, and stalled shapes are the floor of a write coverage plan, and a monitor reconstructs each the same way the eye does: capture AW, collect W beats (with WSTRB) until WLAST, pair the B response by BID, and check it all against AW. Coverage must hit, at minimum: single-beat (AWLEN=0), multi-beat bursts of varied length/size/type, and backpressured writes (independent random WREADY and BREADY delays) — plus the cross with partial WSTRB patterns and the error BRESP cases from 4.5. A plan that only runs unstalled, full-strobe, single-beat writes verifies almost none of the write path.

The waveform shapes also map directly to assertions: WLAST on beat AWLEN+1, stability of WVALID/WDATA/WSTRB under backpressure, B-after-WLAST, exactly one BRESP per write. Because this chapter is where the channels combine, it's where the interactions (a stall mid-burst, a late B after a burst) get exercised — interactions that per-channel tests miss. Mechanics in Module 16.

9. Interview Questions

10. Summary

A write on a waveform is three handshakes to find and reconcile: AW (the contract — address and AWLEN/AWSIZE/AWBURST), the W burst (exactly AWLEN+1 beats, WSTRB per beat, WLAST on the last), and B (one BRESP, paired by BID). The three canonical shapes are the same transaction under different conditions: the single-beat write (AWLEN=0, one beat, one response), the burst write (one AW, many beats, one B, with a legal unbounded gap before B), and the stalled write (backpressure on W, with WVALID/WDATA held stable across the stall — lossless).

Read any of them with one method: find AW, count W to WLAST (= AWLEN+1), check WSTRB, read BRESP/BID — and every Module 4 bug surfaces as the step that disagrees. Verify with these shapes as the floor, crossed with partial strobes, error responses, independent backpressure, and outstanding/out-of-order writes. That completes the write path; Module 5 does the same channel-by-channel walk for the read path, beginning with the AR channel.

11. What Comes Next

That closes Module 4 — Write Transactions. Module 5 walks the read path the same way:

5.1 — The Read Address (AR) Channel (coming next) — every AR signal and how a read is launched.

Previous: 4.5 — BRESP & Write Response Timing. For the broader protocol catalog, see the AMBA family overview doc.

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Standards & specifications

Governing standard: Arm AMBA AXI Protocol Specification (IHI 0022)(opens Arm in a new tab)
Defines the AXI channels, handshake and ordering rules. RTL structure, interconnect topology and verification strategy are design choices this specification does not mandate.

This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.

Where this fits

Part of the AMBA AXI curriculum.