AMBA AXI · Module 17
Waveform-Based Debug Methodology
A single repeatable method for debugging any AXI waveform — classify the symptom (hang vs. wrong-data vs. wrong-response vs. wrong-routing), locate it in time and channel, reconstruct the transaction, compare against intent, and trace to root — integrating every specific technique of Module 17 into one disciplined flow.
Module 17 covered specific AXI bugs — stuck handshakes, missing LAST, wrong LEN/SIZE/WSTRB, response errors, ID mismatches, deadlocks. This final chapter ties them into one repeatable methodology so that, faced with any failing AXI waveform, you have a disciplined flow rather than ad-hoc staring. The method is a decision tree: classify the symptom, which routes you to the right technique; locate it in time and channel; reconstruct the transaction; compare against intent; and trace to root. Every specific chapter slots into one branch. The goal is to make debugging systematic — the same first questions every time, leading to the same kind of localized answer — turning AXI debugging from an art into a procedure you can apply, teach, and trust.
1. The Five-Step Method
Every AXI debug follows the same five steps, regardless of the bug. (1) Classify the symptom — is the bus hung, returning wrong data, returning a wrong response code, or delivering responses to the wrong transaction? (2) Locate — which channel, which cycle, which transaction? (3) Reconstruct — assemble the transaction(s) involved from the beats. (4) Compare against intent — what should have happened (reference model / spec)? (5) Trace to root — follow the discrepancy back to its cause. The classification in step 1 routes the rest: each symptom class points at a specific Module 17 technique.
2. Step 1 — Classify the Symptom (The Routing Decision)
Classification is the highest-leverage step because it routes the entire investigation. Four symptom classes, each pointing at a Module 17 technique: Hang (the bus stops progressing) → stuck handshake (17.1), missing LAST (17.2), or deadlock (17.7), detected via timeouts (17.8). Wrong data (response OKAY, content corrupt) → wrong LEN/SIZE (17.3) or wrong WSTRB (17.4). Wrong response code (SLVERR/DECERR) → response-error tracing (17.5). Wrong routing (correct data, wrong transaction) → ID mismatch (17.6). Getting the class right sends you down the correct branch immediately; misclassifying wastes time in the wrong technique.
3. Steps 2–4 — Locate, Reconstruct, Compare
With the class chosen, locate the failure: timeouts (17.8) localize a hang to a channel/transaction; assertions (16.2) localize a protocol violation to a cycle; the scoreboard (16.4) localizes a data/response/ID mismatch to a transaction. Then reconstruct the involved transaction(s) from the beats (the monitor, 16.3, does this) so you reason in transactions, not raw signals. Then compare against intent — the reference model says what should have happened, and the discrepancy between observed and intended is the bug's signature. This is where the recurring lesson of Module 17 lands: many bugs are internally self-consistent, so only comparison against intent reveals them.
4. Step 5 — Trace to Root, by the Bug's Level of Structure
The final step follows the discrepancy to its cause, and the kind of trace depends on the bug's level of structure — the unifying insight of Module 17. Signal-level bugs (stuck handshake) trace through the handshake dependency (who waits on whom, 17.1). Beat/burst-level bugs (LAST, LEN/SIZE, WSTRB) trace through the burst contract (cross-check against the declared and intended shape, 17.2–17.4). Transaction-level bugs (response codes) trace into the slave or decode (17.5). Inter-transaction (relational) bugs (ID mismatch) trace through transaction-matching (17.6). Global-dependency bugs (deadlock) trace through the wait-for graph and its cycles (17.7). The waveform — annotated with the located failure, the reconstructed transaction, and the intent comparison — is read at the bug's level.
Annotated waveform read at the bug's level
9 cycles5. Common Misconceptions
6. Debugging Insight
7. Verification Insight
8. Interview Questions
9. Summary
AXI debugging is one repeatable five-step method, not a collection of tricks: classify the symptom, locate it, reconstruct the transaction, compare against intent, and trace to root. Classification (step 1) is decisive because it routes everything — the four symptom classes (hang → 17.1/17.2/17.7 via timeouts 17.8; wrong data → 17.3/17.4; wrong response code → 17.5; wrong routing → 17.6) each select a specific technique, the instrumentation to read, and the structural level to read the waveform at. The middle steps run on the Module 16 infrastructure: timeouts and assertions locate, the monitor reconstructs transactions from beats, and the scoreboard's reference model supplies intent and flags the observed-vs-intended discrepancy — so a well-instrumented environment makes debugging fast because locate/reconstruct/compare are already done.
The unifying lens is the bug's level of structure — signal, beat/burst, transaction, inter-transaction relationship, or global dependency — which determines both the detection technique and how the waveform is read, and which the symptom classification exists to identify (a signal-level hang and a global-level deadlock both look like "the bus stopped" but are debugged completely differently). The recurring sub-lesson is that the waveform shows what happened, intent shows what should have — many bugs are internally self-consistent and catchable only by comparison against intent. The deliverable is a mental procedure: same first question every time, routed by class and level, leaning on instrumentation, terminating in a localized, explained, structurally-confirmed root cause. This completes Module 17 (AXI Debugging) — from the specific bug taxonomies (17.1–17.8) to the unified method that subsumes them. Next, Module 18 turns from doing the work to articulating it: interview mastery, where explaining this method clearly is itself the skill under test.
10. What Comes Next
You can now debug any AXI waveform systematically; Module 18 turns to articulating it:
- 18.1 — Beginner Interview Questions (coming next) — the fundamentals interviewers always open with, where explaining AXI concepts (and debugging methods) clearly and correctly is the skill being assessed.
Previous: 17.8 — Timeout Debugging. Related: 17.1 — Stuck VALID / Stuck READY through 17.8 — Timeout Debugging for the specific techniques this method integrates, and 16.1 — The Protocol-Checker Mindset for the verification infrastructure debugging runs on.
Continue learning
Related tutorials
- Related topic
AMBA — AHB · APB · AXI
ARM's AMBA family — channels, handshakes, ordering rules, and verification strategy.
- Related topic
AXI4 Write Channel — AW, W & B Handshake
The AMBA 5 AXI4 write path — AW/W/B channels, the VALID/READY handshake, channel-dependency rules, and BRESP write-response semantics.
- Related topic
Common Handshake Bugs
A field guide to the recurring AXI handshake bugs — dropped VALID, mutated payload, VALID-waits-for-READY deadlock, ordering violations, and undrained responses — and how to spot each.
- Related topic
Stuck VALID / Stuck READY
Diagnose an AXI channel hung on VALID or READY — the two stuck signatures, the decisive question of which side is waiting on which, the combinational VALID-depends-on-READY deadlock, the cross-channel dependency hang, and the systematic waveform-reading method that localizes a stuck handshake to its root cause.
Standards & specifications
- Governing standard
- Arm AMBA AXI Protocol Specification (IHI 0022)(opens Arm in a new tab)
Defines the AXI channels, handshake and ordering rules. RTL structure, interconnect topology and verification strategy are design choices this specification does not mandate.
This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.
Where this fits
Part of the AMBA AXI curriculum.
