AMBA AXI · Module 6

AxLOCK & AxCACHE

Decode the AXI access attributes — AxLOCK (normal vs exclusive, and the AXI3 locked removal) and AxCACHE (the four bufferable/modifiable/allocate bits and the memory types they encode).

Two address-channel signals carry access policy rather than transfer geometry: AxLOCK (is this an exclusive/atomic access?) and AxCACHE (how may the memory system buffer, cache, and merge this access?). They don't change what data moves or where — they change how the system is allowed to treat it. This chapter decodes both: AxLOCK's normal/exclusive encoding (and the AXI3→AXI4 removal of locked), and AxCACHE's four bits and the memory types they form. The full exclusive-access mechanism is Module 9; here we nail the encodings and what each attribute requests.

1. Two Attribute Signals

AxLOCK and AxCACHE are hints/qualifiers on the transaction, not part of its size or address:

AxLOCK says whether the access is exclusive (part of an atomic read-modify-write sequence) or normal.
AxCACHE says how the access may be buffered, cached, and allocated as it travels through the memory system — i.e., its memory type.

Both ride the address channel (AWLOCK/ARLOCK, AWCACHE/ARCACHE) and are constant for the transaction. A simple subordinate (a basic memory or register block) can often ignore them; they matter at the points that implement atomicity (exclusive monitors) and caching/buffering (caches, write buffers, memory controllers).

2. AxLOCK — Exclusive Access

AxLOCK marks an exclusive access — the AXI mechanism for atomic read-modify-write (e.g., a semaphore or lock acquired with load-exclusive / store-exclusive). In AXI4 it is a 1-bit field:

`AxLOCK`	Meaning
`1'b0`	Normal access
`1'b1`	Exclusive access

An exclusive read registers a monitor for that location; an exclusive write succeeds (returning EXOKAY) only if no other agent wrote the location in between — otherwise it fails (returns OKAY, and the store-exclusive reports failure). That monitoring/EXOKAY mechanism is the subject of Chapter 9.3; here the key fact is the encoding and that AxLOCK=1 is what requests exclusivity.

AXI3 difference: AXI3's AxLOCK was 2 bits, encoding normal, exclusive, and locked (a hard bus-locking mode). AXI4 removed locked and shrank AxLOCK to 1 bit (normal/exclusive only) — locked access serialized the interconnect and was deemed not worth its cost. So an AXI3↔AXI4 bridge must reconcile the differing AxLOCK widths and the absence of locked on the AXI4 side.

Figure 1 — AxLOCK encoding. AXI4 uses 1 bit: 0 = normal, 1 = exclusive (atomic read-modify-write, monitored, returns EXOKAY on success). AXI3 used 2 bits and also had a 'locked' mode, which AXI4 removed. Exclusive is the surviving atomicity mechanism.

3. AxCACHE — The Four Memory-Attribute Bits

AxCACHE is a 4-bit field whose bits are individual attributes describing how the access may be treated by the memory system:

Bit	AXI4 name	Meaning
`AxCACHE[0]`	Bufferable	The access may be held in a buffer (the response can come back before it reaches its final destination).
`AxCACHE[1]`	Modifiable	The access may be changed — split, merged, or resized — by the interconnect (e.g., a burst broken up). (Called Cacheable in AXI3.)
`AxCACHE[2]`	Read-Allocate	A cache may allocate a line on this access (read-allocation hint).
`AxCACHE[3]`	Write-Allocate	A cache may allocate a line on this access (write-allocation hint).

The bits are permissions/hints: "Bufferable" lets a write buffer ack early; "Modifiable" lets the interconnect reshape the transaction; the allocate bits hint whether caches should pull the line in. A Device access (a peripheral register) is typically non-modifiable (you must not split/merge an access to a control register), while Normal memory is modifiable and may be cacheable.

Figure 2 — the four AxCACHE bits. Bit 0 Bufferable (response may complete before reaching the destination). Bit 1 Modifiable (interconnect may split/merge/resize the access; non-modifiable for device/peripheral accesses). Bits 2–3 Read-/Write-Allocate (cache allocation hints). The combination encodes the access's memory type.

4. AxCACHE Memory Types

The bit combinations form named memory types. A representative subset (reads and writes have slightly different allocate semantics, but the structure is the same):

`AxCACHE`	Memory type
`4'b0000`	Device Non-bufferable
`4'b0001`	Device Bufferable
`4'b0010`	Normal Non-cacheable Non-bufferable
`4'b0011`	Normal Non-cacheable Bufferable
`4'b1010`	Write-Through No-Allocate
`4'b1110`	Write-Through Read-Allocate
`4'b1011`	Write-Back No-Allocate
`4'b1111`	Write-Back Read- and Write-Allocate

The pattern: Device types (00xx) are non-modifiable and used for peripherals/registers — strongly ordered, never speculatively merged; Normal types (1x modifiable) are for memory and may be cacheable (write-through / write-back) with allocation hints. The higher the type, the more freedom the system has to buffer, cache, and reorder for performance — which is exactly why peripherals must use Device types (you can't cache or merge a control-register write).

5. The Attributes on the Address Channel

AxLOCK and AxCACHE travel with the address handshake, constant for the transaction:

axcache-table — AxLOCK and AxCACHE on the address channel

6 cycles

Figure 3 — AxLOCK and AxCACHE on the address handshake. Here an exclusive access (AxLOCK=1, expecting EXOKAY) to write-back, read+write-allocate memory (AxCACHE=4'b1111). The attributes are driven with the address and held stable through the handshake; they qualify the whole transaction's policy without changing its data or address.

6. Where These Attributes Matter

These signals are ignored by simple endpoints and acted on by the system blocks that implement atomicity and caching:

Figure 4 — where AxLOCK and AxCACHE take effect. AxLOCK drives the exclusive-access monitor (atomics, EXOKAY). AxCACHE drives the memory system: write buffers honor Bufferable, the interconnect honors Modifiable when splitting/merging, and caches use the allocate hints. A basic memory/register slave can ignore both; the system blocks that implement these behaviors must not.

7. Common Misconceptions

Myths to unlearn

"AxLOCK is still 2 bits / AXI4 has locked access." AXI4's AxLOCK is 1 bit (normal/exclusive only); locked was an AXI3 mode that AXI4 removed. Only exclusive survives for atomicity.
"AxCACHE controls whether data is cached, full stop." Its bits are hints/permissions (bufferable, modifiable, allocate) that the memory system may act on — not a direct cache-enable. A subordinate without caches/buffers can ignore them.
"Device and Normal memory are interchangeable." No — Device accesses (peripheral registers) must be non-modifiable and non-cacheable (no merging/splitting/caching), while Normal memory may be cached and reshaped. Marking a control register as Normal/cacheable is a correctness bug.
"Bufferable means the data is buffered somewhere I must track." Bufferable means the response may return early (before the write reaches its final destination) — a performance permission, not a requirement to inspect a buffer.
"These signals change the data or address." They don't — AxLOCK/AxCACHE are policy qualifiers (atomicity, memory type); the data and address are unchanged.

8. Debugging Insight

🔍 Debugging insight — attribute mismatches cause subtle, non-obvious bugs

AxLOCK/AxCACHE bugs rarely look like "wrong data on the bus" — they show up as ordering, coherency, or atomicity anomalies:

A peripheral register behaving erratically (writes lost, reads stale, accesses reordered)? Check AxCACHE — if the access is marked Modifiable/Bufferable/Cacheable (a Normal type) when it should be a Device type, the interconnect may merge/split/buffer it or a cache may hold it, which is illegal for a control register. Device registers must use a Device AxCACHE (00xx).
An exclusive/atomic sequence never succeeds (or always does)? Check AxLOCK — the exclusive read and write must both be marked AxLOCK=1, hit a location an exclusive monitor covers, and you must read the EXOKAY/OKAY response correctly (Chapter 9.3). A normal access (AxLOCK=0) where exclusive was intended silently breaks atomicity.
Early write completion surprising you? A Bufferable access lets the response return before the write lands at its destination — correct behavior, but if your code assumed the write was globally visible at B, that's the attribute talking.
AXI3↔AXI4 bridge atomics broken? The AxLOCK width differs (2-bit vs 1-bit) and locked is gone in AXI4 — a bridge that mishandles this breaks exclusive/locked semantics across the boundary.

So: erratic peripheral → wrong AxCACHE (should be Device); broken atomics → AxLOCK/exclusive-monitor/EXOKAY handling. The data path can look perfect while the policy is wrong.

9. Verification Insight

✅ Verification insight — attribute legality and consistency, plus exclusive sequences

Verifying these attributes is about legality and consistency, since they qualify policy rather than data. Checks: a memory region's accesses carry the expected memory type (peripheral regions → Device AxCACHE; cacheable memory → Normal types) — a scoreboard/region model can flag a control register accessed as cacheable; AxLOCK is within the version's width (1-bit AXI4, 2-bit AXI3) and not the removed locked value on AXI4; and exclusive accesses are well-formed (exclusive read paired with exclusive write to the same location/size, within the exclusive-access size/alignment limits — detail in 9.3). Coverage wants each AxCACHE memory type observed, both AxLOCK values, and complete exclusive sequences ending in both EXOKAY (success) and OKAY (failure, when the monitor was cleared by an intervening write).

Negative/interaction testing matters: deliberately race an intervening write into an exclusive sequence and assert the store-exclusive fails (returns OKAY, not EXOKAY); and verify Device-typed accesses are not merged/reordered by the interconnect. These are the bugs functional data-checking misses. Exclusive-access mechanics and full coverage are Module 9 / Module 16.

10. Interview Questions

11. Summary

AxLOCK and AxCACHE are policy qualifiers on the address channel — they change how the system may treat an access, not its data or address. AxLOCK marks exclusive (atomic read-modify-write) vs normal access — 1 bit in AXI4 (0 normal, 1 exclusive, success = EXOKAY), where AXI3's 2-bit field and its locked mode were removed. AxCACHE is 4 bits — Bufferable (early response), Modifiable (interconnect may split/merge/resize), and Read/Write-Allocate (cache hints) — combining into memory types: Device (00xx, non-modifiable, for peripherals) through Normal cacheable (write-through/back, for memory).

The practical weight is that these qualify correctness-relevant policy: a peripheral register must use a Device AxCACHE (never cacheable/modifiable), and atomicity requires AxLOCK=1 on both halves plus correct EXOKAY/OKAY handling. Their bugs look like coherency/ordering/atomicity anomalies, not bus errors — so debug and verify them as memory-type and exclusive-sequence legality, separate from data integrity. Next: AxPROT, AxQOS, and AxREGION — protection, quality-of-service, and region attributes.

12. What Comes Next

You've decoded the lock and cache attributes; next, the protection/QoS/region attributes:

6.5 — AxPROT, AxQOS & AxREGION (coming next) — protection (privilege/secure/instruction), QoS priority, and region identifiers, and their system use.
6.6 — AxUSER & Sideband Signals (coming soon) — user-defined sideband and its integration risks.

Previous: 6.3 — AxID. For the broader protocol catalog, see the AMBA family overview doc.

Continue learning

Standards & specifications

Governing standard: Arm AMBA AXI Protocol Specification (IHI 0022)(opens Arm in a new tab)
Defines the AXI channels, handshake and ordering rules. RTL structure, interconnect topology and verification strategy are design choices this specification does not mandate.

This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.

Where this fits

Part of the AMBA AXI curriculum.