AMBA AXI · Module 20

AXI Interview Checklist

A last-mile revision checklist before an AXI interview — the must-know fundamentals, the most-probed handshake and ordering rules, the design and verification points, and the high-frequency questions and myths, distilled into a final pre-interview pass so you walk in able to articulate the essentials crisply.

The previous checklists are for building — this one is for you, the night before an AXI interview. The AXI interview checklist is a last-mile revision list: the must-know points distilled into a final pass so the essentials are fresh and articulable. It's not for learning AXI (Modules 1–18 did that) — it's for revision: a compact set of the highest-frequency, highest-impact items to refresh before you walk in, organized so you can self-check ("can I state the handshake rule crisply? the ordering rules? size outstanding depth?"). This chapter distills the interview-mastery module (18) and the whole curriculum into a final pre-interview pass: the fundamentals, the most-probed rules, the design/verification essentials, and the myths to never state.

1. The Must-Know Fundamentals

Refresh the foundation — the answers you must give instantly. What AXI is: a high-performance AMBA bus that decouples address from data and supports multiple outstanding, out-of-order transactions, for high throughput. The five channels: AW, W, B (write) and AR, R (read) — independent, each with a VALID/READY handshake. The handshake: a beat transfers when both VALID and READY are high on a rising edge; payload held stable until accepted. Reads vs. writes: writes use three channels with one aggregated B; reads use two channels with per-beat RRESP. If any of these isn't instant and crisp, revise it first — they're the warm-up filters that gate everything else.

Figure 1 — the must-know fundamentals to refresh first. What AXI is (decoupled address/data, multiple outstanding/out-of-order, high throughput); the five channels (AW/W/B + AR/R, independent, VALID/READY each); the handshake (both high on a rising edge = transfer, payload held stable); reads vs. writes (3 channels/one B vs. 2 channels/per-beat RRESP). These are the warm-up filters that gate the interview — if any isn't instant and crisp, revise it first, because a vague fundamental ends the interview before the harder questions.

2. The Most-Probed Rules

These are the items interviewers push hardest — know each cold with its why. The handshake asymmetry (the #1 probe): READY may depend on VALID, but VALID must never depend combinationally on READY — else deadlock. The ordering rules: same-ID responses in order, different-ID in any order — and IDs are what enable out-of-order completion. The 4 KB rule: a burst must not cross a 4 KB boundary, because that's the minimum page size (one slave/one set of attributes). Burst span: (LEN+1) << SIZE; per-beat increment 1 << SIZE. WSTRB: per-byte write-enable for partial writes. For each, rehearse the crisp statement and the one-level-deeper why, because that's exactly where the interviewer probes.

Figure 2 — the most-probed rules, to know cold with their why. The handshake asymmetry (#1 probe: READY may depend on VALID, VALID must never depend on READY — deadlock otherwise); ordering rules (same-ID in order, different-ID free; IDs enable out-of-order); the 4 KB rule (no burst crosses a page — minimum page size); burst span ((LEN+1) << SIZE, increment 1 << SIZE); WSTRB (per-byte enable for partial writes). Rehearse each as a crisp statement plus the one-level-deeper why, because that's where the interviewer pushes.

3. The Design and Verification Essentials

Refresh the build-and-prove points for design/verification questions. Design: the structured approach (clarify → interface → FSM → handshake → corners); the canonical blocks (AXI4-Lite slave = two FSMs; skid buffer = two registers, the minimum for fully-registered full-throughput); the instincts (channel independence, VALID⊥READY, corner-awareness, reuse). Verification: the four layers (assertions = compliance, monitor = reconstruct, scoreboard = correctness, coverage = completeness); the two distinctions (compliance ≠ correctness, checking ≠ coverage). Performance: bandwidth = width × frequency × efficiency; Little's Law (outstanding ≈ bandwidth × latency); latency and throughput decoupled by outstanding. These cover the design, verification, and performance question rounds.

Figure 3 — the design, verification, and performance essentials. Design: structured approach (clarify→interface→FSM→handshake→corners), canonical blocks (Lite slave = two FSMs, skid = two registers), instincts (channel independence, VALID⊥READY, corner-awareness, reuse). Verification: four layers (assertions/monitor/scoreboard/coverage) and two distinctions (compliance≠correctness, checking≠coverage). Performance: bandwidth = width × frequency × efficiency, Little's Law (outstanding ≈ bandwidth × latency), latency/throughput decoupled by outstanding. These cover the design, verification, and performance rounds.

4. The Myths to Never State, and the Delivery

Finally, refresh the myths to never state (the confident-wrong traps) and the delivery discipline. The myths: "VALID waits for READY" (no — the asymmetry), "all responses ordered" (no — same-ID only), "a clean checker means verified" (no — compliance ≠ correctness), "high latency = low throughput" (no — decoupled by outstanding), "exclusive locks the bus" (no — that's locked access). The delivery: lead with the precise core, add the why, stop, go deeper on probe; avoid rambling and vague-but-confident; and when unsure, reason aloud from a known principle rather than guessing. A confident-wrong answer is the worst outcome — knowing the myths and the calibrated-reasoning habit is your insurance.

Figure 4 — the myths to never state and the delivery discipline. Myths (confident-wrong traps): VALID waits for READY (→ asymmetry), all responses ordered (→ same-ID only), clean checker = verified (→ compliance ≠ correctness), high latency = low throughput (→ decoupled by outstanding), exclusive locks the bus (→ that's locked). Delivery: lead with the precise core, add the why, stop, go deeper on probe; avoid rambling/vague-but-confident; when unsure, reason aloud from a principle. A confident-wrong answer is the worst outcome — the myths plus calibrated reasoning are the insurance.

5. Common Misconceptions

Myths to unlearn

"Cramming new material the night before helps." The interview checklist is for revision, not learning — refresh what you already know so it's fresh and articulable. Trying to learn new AXI material last-minute crowds out the fundamentals you need instant; revise the essentials instead.
"Skip the fundamentals — focus on hard topics." The fundamentals are filters — a vague answer to "what's the handshake?" ends the interview before the hard topics. Revise the fundamentals first and most, because their failure cost is highest and their familiarity tempts you to under-prepare them.
"Memorizing answers is enough." Interviewers probe the why, so for each item revise the crisp core and the one-level-deeper reason (handshake → why-asymmetry → deadlock). Memorized phrases collapse under the first probe; understanding the why holds up.
"Confidence always helps." A confident-wrong answer is the worst outcome — it signals you can't tell what you know from what you don't, undermining everything. Better to reason aloud from a principle when unsure; calibrated uncertainty beats false confidence.
"The checklist is a script to recite." It's a self-check, not a script — go through it asking "can I state this crisply, with the why?", and revise whatever you can't. The interview itself requires adapting to the actual questions, using the refreshed essentials, not reciting a memorized list.
"Once revised, you're done." Revise, but also rehearse the delivery (lead-core-add-why-stop) and the calibrated-reasoning habit — knowing the content isn't the same as articulating it well under pressure, which is the actual skill the interview tests.

6. Debugging Insight

🔍 Debugging insight — self-check the checklist and patch the weak spots

Use the checklist as a self-diagnostic the day before — for each item, test yourself and patch what's weak:

Can't state a fundamental instantly? (What's AXI? the channels? the handshake?) — Highest priority to patch; these are the filters. Revise until each is instant and crisp.
Stumble on the handshake asymmetry? The #1 probe — drill "READY may depend on VALID, VALID must never depend on READY, else deadlock" until it's automatic, with the why.
Reverse the ordering rule? (Said "all ordered" or "different-ID ordered"?) — Re-anchor on "same-ID ordered, different-ID free; IDs enable out-of-order." This is commonly reversed.
Can't compute a burst span or outstanding depth? Drill (LEN+1) << SIZE and Little's Law (outstanding ≈ bandwidth × latency) — interviewers ask quick calculations.
Conflate compliance and correctness, or checking and coverage? Re-fix the two verification distinctions — they're the most-probed verification concepts and easy to blur.
Catch yourself about to state a myth? Note which one and pair it with its correction so you'd never say it (e.g. "exclusive locks the bus" → "no, exclusive is non-locking").

The method: self-check every item, patch the weak ones, rehearse the delivery. The checklist surfaces your gaps the day before, when there's still time to refresh them — turning "I hope I remember" into "I confirmed I can state each essential crisply." Spend the most time on the highest-impact, easiest-to-miss items (fundamentals, the asymmetry, the ordering rule, the two distinctions, the myths).

7. Verification Insight

✅ Interview insight — revise the essentials, rehearse the delivery, and walk in able to articulate, not recite

The AXI interview checklist is the last-mile revision pass — not learning (the curriculum did that), but refreshing the highest-frequency, highest-impact items so they're fresh and articulable when you walk in. The content to revise, by round: fundamentals (what AXI is, the five channels, the handshake, reads vs. writes — the warm-up filters); most-probed rules (the handshake asymmetry as the #1, the same-ID/different-ID ordering, the 4 KB rule, the burst-span and Little's-Law formulas, WSTRB); design/verification/performance essentials (the design approach and canonical blocks, the four verification layers and two distinctions, the bandwidth/Little's-Law performance reasoning); and the myths to never state with their corrections. Three disciplines for the final pass: (1) Revise, don't cram — refresh what you know rather than learning new material last-minute, prioritizing the fundamentals (highest failure cost, most tempting to under-prepare) and the most-probed rules. (2) Revise the why, not just the what — interviewers probe the reason behind every fundamental, so for each item have the crisp core and the one-level-deeper why (handshake → asymmetry → deadlock), since memorized phrases collapse on the first probe. (3) Rehearse the delivery and the calibrated-reasoning habit — lead with the precise core, add the why, stop, go deeper on probe; avoid rambling and vague-but-confident; and when genuinely unsure, reason aloud from a known principle rather than guessing, because a confident-wrong answer is the worst outcome and calibrated uncertainty is a strength. The meta-point that ties Module 18 to this checklist: the interview tests articulation of genuine understanding, not recall, so the checklist is a self-check of whether you can state each essential crisply with its why — not a script to recite — and the real preparation is the understanding the whole curriculum built, of which this is the final refresh. Use it the day before to surface and patch your weak spots (the items you can't state instantly), rehearse the delivery, and walk in able to articulate the essentials — the fundamentals crisply, the rules with their why, the design/verification/performance reasoning structured, and the myths avoided. That readiness — refreshed essentials plus practiced delivery plus the calibrated-reasoning habit — is what the interview checklist delivers, and it's the operational complement to the deep understanding Modules 1–19 built. The final chapter distills the single most valuable list: the common mistakes to never make, in design, verification, and interviews alike.

8. Interview Questions

9. Summary

The AXI interview checklist is the last-mile revision pass — for refreshing, not learning — distilling the highest-frequency, highest-impact items so they're fresh and articulable. Revise by round: fundamentals (what AXI is, the five channels, the handshake, reads vs. writes — the warm-up filters to have instant); most-probed rules (the handshake asymmetry as the #1 — READY may depend on VALID, VALID must never depend on READY, else deadlock; same-ID ordered / different-ID free; the 4 KB rule; burst span (LEN+1) << SIZE; Little's Law; WSTRB); design/verification/performance essentials (the design approach and canonical blocks; the four verification layers and two distinctions — compliance≠correctness, checking≠coverage; bandwidth = width × frequency × efficiency and latency/throughput decoupled by outstanding); and the myths to never state (VALID-waits-for-READY, all-ordered, checker=verified, latency=throughput, exclusive-locks-the-bus) with their corrections.

The disciplines: revise, don't cram (refresh what you know, prioritizing fundamentals — highest failure cost, most tempting to skip); revise the why, not just the what (interviewers probe the reason; memorized phrases collapse on the first probe); and rehearse the delivery and calibrated-reasoning habit (lead-core-add-why-stop; when unsure, reason aloud from a principle rather than guessing, since confident-wrong is the worst outcome). Use the checklist as a self-check the day before — test each item, patch your weak spots, rehearse delivery — because the day-before bottleneck is recall-and-articulation, not understanding, and readiness is articulation-of-understanding-under-pressure, a distinct skill from the knowledge itself. This is the operational complement to the deep understanding Modules 1–19 built and the communication Module 18 taught: walk in with the essentials fresh, the why ready, the calculations drillable, the myths avoided, and the delivery practiced. Next, the final chapter distills the single most valuable list — the common mistakes to never make, across design, verification, and interviews alike.

10. What Comes Next

You're now interview-ready; the final chapter is the most valuable list of all:

20.5 — Common Mistakes Checklist (coming next) — the recurring AXI mistakes to never make, in design, verification, debugging, and interviews — the curriculum's closing distillation of what most often goes wrong and how to avoid it.

Previous: 20.3 — AXI Integration Checklist. Related: 18.1 — Beginner Interview Questions for the fundamentals, 18.8 — Tricky Misconceptions for the myths, and 3.5 — Handshake Dependency & Deadlock Rules for the #1-probed asymmetry.

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Standards & specifications

Governing standard: Arm AMBA AXI Protocol Specification (IHI 0022)(opens Arm in a new tab)
Defines the AXI channels, handshake and ordering rules. RTL structure, interconnect topology and verification strategy are design choices this specification does not mandate.

This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.

Where this fits

Part of the AMBA AXI curriculum.