Tcl · Module 22

Libraries and Parasitics

Cell delay comes from the libraries; wire delay comes from the parasitics. Leave the parasitics out and the tool does not leave wire delay out — it guesses, and does not say so in the report.

Intermediate15 min readtcledapart-iistalibrariesparasiticscorners

Part II · Module 22 · Chapter 22.3 · Libraries and Parasitics

Timing analysis adds up two kinds of delay: through the cells, and along the wires between them. The libraries supply the first and the parasitics supply the second.

Chapter 21.4 covered libraries for synthesis, and the argument is the same here — which libraries, at which corner, checked before the run, recorded afterwards. This chapter does not repeat it. What is new in STA is the second half.

1. Both halves of the delay

Cell delay — how long a gate takes to switch, as a function of input slew and output load. From the library.
Wire delay — how long the signal takes along the interconnect, which depends on resistance and capacitance. From the extracted parasitics.

In older, larger technologies cell delay dominated and wire delay was a correction. In modern nodes it is routinely the other way round, which is why the parasitics are not an optional refinement.

2. Libraries: the same discipline as synthesis

Briefly, because Chapter 21.4 has it in full:

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Snippet

proc check_libraries {paths} {
    set missing {}
    foreach p $paths { if {![file isfile $p]} { lappend missing $p } }
    if {[llength $missing]} {
        error "[llength $missing] library file(s) missing: [join $missing {, }]" \
              {} [list LIB MISSING $missing]
    }
    return [llength $paths]
}

Check before the run, print what you used, record it in the log. The one thing worth adding here: at signoff the libraries should be compared against the ones synthesis used, from the provenance record in Chapter 22.2 §3. A difference is not necessarily wrong, but it should be a decision.

3. Parasitics

Parasitics are the extracted resistance and capacitance of the actual routed wires, produced after place-and-route and supplied per corner.

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Snippet

proc spef_for {corner} { return [file join $::SPEFDIR ${::TOP}_${corner}.spef] }

set spef [spef_for $CORNER]
if {![file isfile $spef]} {
    puts stderr "  WARNING no parasitics for the $CORNER corner: [file tail $spef]"
} else {
    read_parasitics $spef        ;# a tool command
    puts "  parasitics: [file tail $spef]"
}

The per-corner path comes from the helper in Chapter 22.1 §2, which is what makes Chapter 22.8's loop possible.

4. What is assumed when they are missing

The registry purpose's question, and the answer is the thing to take from this chapter.

Missing parasitics do not mean "no wire delay". They mean the tool substitutes an estimate.

With no extracted data, a tool falls back to a model — a wire-load model, a default capacitance per unit, or something similar depending on the tool and settings. It then produces a complete timing report, with numbers for every path, and nothing in the report says the wire delay was guessed.

Three consequences:

The numbers can be wrong in either direction. An optimistic estimate gives slack that does not exist; a pessimistic one sends people chasing paths that are fine.
The error is not uniform. Estimates are worst on exactly the nets that matter — long ones, high-fanout ones (Chapter 19.4) — so the paths most likely to be wrong are the ones you are most likely to be looking at.
It is invisible. The report looks identical to one built on real extraction.

So pre-layout timing is a useful estimate and never a signoff. The distinction has to be recorded, because the two reports look the same.

That is why the warning above goes to stderr and into the log, and why Chapter 22.9's review treats missing parasitics as a finding rather than a detail.

5. The corner must be coherent

Here is the check that is specific to this chapter.

Three things carry a corner: the libraries, the parasitics, and the corner you declared. All three must agree.

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Snippet

proc check_corner_coherence {corner libs spef} {
    set problems {}
    foreach l $libs {
        if {![string match *${corner}* [file tail $l]]} {
            lappend problems "library [file tail $l] does not look like the $corner corner"
        }
    }
    if {$spef ne "" && ![string match *${corner}* [file tail $spef]]} {
        lappend problems "parasitics [file tail $spef] does not look like the $corner corner"
    }
    return $problems
}

6. Recording what was used

Everything in this chapter ends up in the same place: the log, and the run's record.

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Snippet

puts "  corner     : $CORNER"
puts "  libraries  : [llength $LIBS] file(s)"
foreach l $LIBS { puts "      [file tail $l]" }
puts "  parasitics : [expr {$spef eq "" ? "<none — wire delay estimated>" : [file tail $spef]}]"

That last line is the important one. A timing report whose log says <none — wire delay estimated> is interpretable; one that simply does not mention parasitics is not, and six months later nobody can tell which kind of run it was.

7. Exercises

Exercise 1. Which part of the delay comes from the libraries, and which from the parasitics?

Exercise 2. Why are parasitics not an optional refinement in modern nodes?

Exercise 3. What does a tool do when parasitics are missing?

Exercise 4. Why is the error from estimated wire delay not uniform across paths?

Exercise 5. Why can pre-layout timing never be signoff, and what makes that easy to forget?

Exercise 6. Name the three things that carry a corner, and what mixing them produces.

Exercise 7. What are the limits of the filename-based corner check?

Answers.

1. Cell delay — how long a gate takes to switch — comes from the libraries. Wire delay along the interconnect comes from the parasitics.

2. Because wire delay routinely dominates cell delay at modern nodes, so leaving it to an estimate leaves the larger term to a guess.

3. It substitutes an estimate — a wire-load model or similar — and produces a complete report with nothing marking the wire delay as guessed.

4. Because estimates are worst on long and high-fanout nets, which are exactly the paths most likely to be critical and therefore most likely to be the ones you are examining.

5. Because the wire delay is estimated rather than extracted. It is easy to forget because the report is indistinguishable from one built on real extraction.

6. The libraries, the parasitics and the declared corner. Mixing them produces numbers that are each individually valid and describe no physical situation.

7. It depends on the corner name appearing in the filename, which is a convention rather than a fact. Where the tool can report a library's characterisation corner, that is authoritative.

Remember.

Libraries give cell delay; parasitics give wire delay. In modern nodes the second often dominates.
The library discipline is the same as synthesis — check, print, record — plus comparing against the provenance at signoff.
Missing parasitics are replaced by an estimate, not by nothing.
The report does not say the wire delay was guessed, and the estimate is worst on exactly the critical nets.
So pre-layout timing is an estimate, never signoff — and the two reports look identical.
Libraries, parasitics and the declared corner must all agree. Mixing them is silent and meaningless.
A filename check for corner coherence is a cheap heuristic; the tool's own report of a library's corner is authoritative.
Log the parasitics explicitly, including when there are none, so the run is interpretable later.

Where this fits

Part of the Tcl curriculum.