Tcl · Module 20

Output Delays

An output delay is the mirror of an input delay: it reserves the part of the cycle the receiver still needs. Get the two wrong and the budget does not add up — usually in somebody else's favour.

Intermediate16 min readtcledapart-iisdcoutput-delaytimingbudget

Part II · Module 20 · Chapter 20.4 · Output Delays

Data leaving a block is not finished. It still has to travel to whatever captures it and arrive in time to satisfy that flop's setup requirement.

An output delay reserves that part of the cycle. Where an input delay says how much was already used before the data reached you, an output delay says how much must remain after it leaves.

1. The declaration

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

set_output_delay 0.3 -clock core_clk [get_ports {d_out[*]}]

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

=== output delays applied ===
    d_out[0]     clock core_clk   0.3
    d_out[1]     clock core_clk   0.3

The same shape as an input delay — a value, a clock, and a collection — applied to the whole output bus in one command.

2. The mirror

The two constraints describe the same cycle from opposite ends, and holding them as one model is easier than remembering two rules:

	Input delay	Output delay
Describes	the sender's launch	the receiver's capture
Time it accounts for	already used before arrival	still needed after departure
Reduces	the budget for your logic	the budget for your logic
Missing default	data arrives at the edge	the full cycle is available to leave

The last row is the important symmetry: both defaults are optimistic. An output with no delay declared is analysed as though the receiver needs nothing — the whole period is available to get the signal out of your block, which is never true.

3. Where the number comes from

The receiver's requirement, which is the sum of:

the flop's setup time at the far end,
the interconnect delay between the blocks,
and any clock skew between the two domains that has to be covered.

Like the input delay, it should be a number agreed at the interface, written down outside the SDC. The two sides must use the same split — §5 is what happens when they do not.

4. As a fraction, again

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

set PERIOD   2.0
set OUT_FRAC 0.15
set_output_delay [expr {$PERIOD * $OUT_FRAC}] -clock core_clk [get_ports {d_out[*]}]

Same reasoning as Chapter 20.3 §4. When the period changes the reservation follows, and a literal does not.

5. Make the budget add up

This is the part worth taking seriously, and it is three lines of ordinary Tcl in the constraints file itself:

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

set in_frac 0.20 ; set out_frac 0.15
puts [format "    input  %.2f  (%.0f%% of %.1f)" [expr {$PERIOD*$in_frac}]  [expr {$in_frac*100}]  $PERIOD]
puts [format "    output %.2f  (%.0f%% of %.1f)" [expr {$PERIOD*$out_frac}] [expr {$out_frac*100}] $PERIOD]
puts [format "    left for logic inside the block: %.2f (%.0f%%)" \
    [expr {$PERIOD*(1.0-$in_frac-$out_frac)}] [expr {(1.0-$in_frac-$out_frac)*100}]]

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

=== the budget split, stated explicitly ===
    input  0.40  (20% of 2.0)
    output 0.30  (15% of 2.0)
    left for logic inside the block: 1.30 (65%)

6. When the two sides disagree

The interface between two blocks has two constraints describing it: your output delay, and the receiver's input delay. They are supposed to be consistent.

When they are not, the gap is silent in both directions:

Your output delay is smaller than their input delay. You reserved 0.2 for them; they are assuming 0.4 was used getting to them. Someone is 0.2 short, and both reports look clean because each block is meeting its own stated constraint.
Both are generous. You reserve 0.4 and they assume 0.2. Nothing fails; you simply both worked harder than necessary, and somebody paid for area or power to meet a budget that did not exist.

Neither shows up as a violation. The only way to catch it is to check that the numbers at the two ends of an interface agree — which means they have to be recorded somewhere both blocks can see, and ideally derived from one shared file.

A shared constraint include is the usual answer, and it is just a source away (Chapter 15.1):

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

# interface_budget.tcl — one definition, read by both blocks
set IFACE_PERIOD   2.0
set IFACE_IN_FRAC  0.20
set IFACE_OUT_FRAC 0.15

Both constraints files source it; neither has a literal. That the two agree is then structural rather than something somebody has to check.

7. Which outputs need one

Every output. There is no equivalent of the clock-port exception from Chapter 20.3 §7 — a clock going out of a block is itself constrained differently, but an output carrying data always needs its budget reserved.

The check is the same one Chapter 20.8 runs:

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

  ERROR   2 output port(s) with no output delay: d_out[0], d_out[1]

And the same rule applies as for inputs: if an output genuinely does not need timing — a debug pin nobody samples — that is a false path with a reason, not an omission.

8. Exercises

Exercise 1. What does an output delay reserve, and for whom?

Exercise 2. State the mirror relationship between input and output delays in one sentence.

Exercise 3. What is assumed about an output with no delay declared?

Exercise 4. Why are missing output delays more common than missing input delays?

Exercise 5. Your input is 20% and your output is 15%. What is left, and why does printing it matter?

Exercise 6. Your output delay is 0.2 and the receiver's input delay is 0.4. What happens, and does either report show a violation?

Exercise 7. How do you make the two ends of an interface agree structurally?

Answers.

1. The part of the cycle the receiving block still needs — its flop's setup time, the interconnect delay, and any clock skew to be covered.

2. An input delay says how much of the cycle was already used before the data reached you; an output delay says how much must remain after it leaves.

3. That the receiver needs nothing — the entire period is available to get the signal out of the block, which is never true.

4. Because an input obviously needs constraining, while an output feels like the next block's problem. It is not: a path unconstrained at both ends is timed by nobody.

5. 65% for the logic inside the block. Printing it turns an accidental budget into a stated decision somebody can object to early.

6. Someone is 0.2 ns short, and neither report shows a violation, because each block is meeting its own stated constraint. The gap only exists between them.

7. Put the period and the fractions in one shared file that both constraints files source, so neither contains a literal and agreement is structural.

Remember.

An output delay reserves the receiver's share of the cycle — setup, interconnect, and skew.
It is the mirror of an input delay: one accounts for time already used, the other for time still needed.
Both missing defaults are optimistic. No output delay means the receiver is assumed to need nothing.
Missing output delays are the commoner omission, because outputs feel like somebody else's problem.
Express it as a fraction of the period, like the input delay.
Print the leftover budget — the percentage left for logic inside the block is a decision, not a residue.
Disagreement between the two ends is silent in both directions and appears as a violation in neither.
Share one budget file that both constraints files source, so agreement is structural.
Every output needs one; a genuinely untimed output is a false path with a reason, not an omission.

Where this fits

Part of the Tcl curriculum.