Blocking vs Non-Blocking Assignments

// ── Blocking (=): sequential execution ──────────────────────────
always_comb begin
    a = b + 1;     // a is immediately b+1
    c = a * 2;     // c uses the NEW value of a → c = (b+1)*2
end
 
 
// ── Non-blocking (<=): all RHS captured first ───────────────────
always_ff @(posedge clk) begin
    a <= b + 1;    // schedules a = b+1 for end of time step
    c <= a * 2;    // uses OLD value of a (before posedge) → c = a_old*2
end
// Both a and c update simultaneously at end of time step.
// This is exactly how flip-flops work in real hardware.
 
 
// ── The classic swap: only non-blocking works without a temp ────
always_ff @(posedge clk) begin
    a <= b;         // schedule: a ← old b
    b <= a;         // schedule: b ← old a
end
// Result: a and b are swapped. No temp variable needed.
 
// ── With blocking = the swap fails ──────────────────────────────
always_ff @(posedge clk) begin
    a = b;          // a is immediately b — old a is LOST
    b = a;          // b = b (the same value!) — swap broken
end

// ── CORRECT: = in always_comb ───────────────────────────────────
always_comb begin
    sum    = a + b;         // purely combinational
    carry  = sum[8];        // uses updated sum immediately
    result = sum[7:0];
end
 
 
// ── CORRECT: <= in always_ff ─────────────────────────────────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        q     <= '0;
        count <= '0;
    end else begin
        q     <= d;
        count <= count + 1;
    end
end
 
 
// ── WRONG: = in always_ff ────────────────────────────────────────
always_ff @(posedge clk) begin
    q = d;      // ⚠ blocking in clocked block — race condition risk
end
// Simulates correctly when only one always_ff drives q.
// Breaks silently if two always_ff blocks both assign q.
 
 
// ── WRONG: <= in always_comb ─────────────────────────────────────
always_comb begin
    out <= a | b;  // ⚠ NBA in comb: out updates at end of delta, not now
                   // subsequent uses of out see the OLD value
end

// ── Classic race: shift register with blocking ──────────────────
// WRONG — outcome depends on which always_ff the simulator runs first
always_ff @(posedge clk) a = d_in;   // ⚠ blocking
always_ff @(posedge clk) b = a;      // ⚠ which 'a'? old or new?
 
// If 'a' block runs first: b captures the NEW a (= d_in) — acts like wire
// If 'b' block runs first: b captures the OLD a — acts like flip-flop
// Synthesis always infers a flip-flop. Simulation may not match.
 
 
// ── CORRECT: non-blocking eliminates the race ───────────────────
always_ff @(posedge clk) a <= d_in;   // schedules NBA
always_ff @(posedge clk) b <= a;      // RHS sampled before NBA region
 
// Both RHS values captured in Phase 1 (a_old, b_old).
// Both LHS updated in Phase 2: a = d_in, b = a_old.
// Deterministic regardless of block evaluation order. Matches hardware.

// ─────────────────────────────────────────────────────────────────────────────
//  Three shift registers, identical intent:
//    A: blocking, "producer" block written first
//    B: blocking, "consumer" block written first   <- same logic, swapped text
//    C: non-blocking (correct)
//
//  A and B differ only in the order two concurrent always_ff blocks appear in
//  the file. If they disagree, the result was never in the logic.
//
//  vcs -sverilog nba_race_proof.sv && ./simv
//  xrun -sv nba_race_proof.sv     |     iverilog -g2012 -o r nba_race_proof.sv && ./r
// ─────────────────────────────────────────────────────────────────────────────
module nba_race_proof;
 
  timeunit 1ns; timeprecision 1ps;
 
  logic clk = 1'b0, d = 1'b0;
  logic a1, a2, b1, b2, c1, c2;
  int   errors = 0;
 
  always #5 clk = ~clk;
 
  // ── A: blocking, producer first ───────────────────────────────────────
  always_ff @(posedge clk) a1 = d;      // producer
  always_ff @(posedge clk) a2 = a1;     // consumer - which a1?
 
  // ── B: blocking, consumer first. Same two blocks, swapped in the file. ─
  always_ff @(posedge clk) b2 = b1;     // consumer
  always_ff @(posedge clk) b1 = d;      // producer
 
  // ── C: non-blocking. Order cannot matter: all RHS sample before any LHS
  //      updates, so both blocks read pre-edge values whatever the order.
  always_ff @(posedge clk) c1 <= d;
  always_ff @(posedge clk) c2 <= c1;
 
  initial begin
    // Drive a single 1 through the shift register and watch stage 2.
    @(negedge clk) d = 1'b1;
    @(negedge clk) d = 1'b0;            // one-cycle pulse
    @(posedge clk);                      // edge 2: a true 2-stage sees it now
    #1;
 
    $display("  after two edges:  a2=%0b   b2=%0b   c2=%0b", a2, b2, c2);
    $display("");
 
    // C is the only version with a defined answer, so C is the only one
    // checked. Asserting a specific result for A or B would encode one
    // simulator's arbitrary scheduling choice as if it were the specification.
    if (c2 !== 1'b1) begin
      errors++;
      $display("  ** FAIL: non-blocking stage 2 did not see the pulse");
    end
 
    if (a2 !== b2)
      $display("  ** A and B DISAGREE. Identical logic, opposite answers - the\n"
               "     only difference is which block was typed first.");
    else
      $display("  ** A and B agreed on THIS simulator. That is luck, not a\n"
               "     guarantee: nothing in IEEE 1800 orders these two blocks.");
 
    $display("  ** C is order-independent by construction.");
    if (errors == 0) $display("\n  [PASS] non-blocking behaved as a 2-stage pipeline");
    else             $display("\n  [FAIL] %0d check(s) failed", errors);
    $finish;
  end
 
endmodule

  after two edges:  a2=1   b2=0   c2=1
 
  ** A and B DISAGREE. Identical logic, opposite answers - the
     only difference is which block was typed first.
  ** C is order-independent by construction.
 
  [PASS] non-blocking behaved as a 2-stage pipeline

// ── Mistake 1: mixing = and <= in the same always_ff ────────────
always_ff @(posedge clk) begin
    temp = a + b;    // ⚠ blocking — tool-dependent, lint error
    out  <= temp;    // ⚠ uses immediately-updated temp — breaks NBA model
end
 
// FIX: split into comb + ff, or use NBA throughout
always_comb temp = a + b;           // combinational intermediate
always_ff @(posedge clk) out <= temp;
 
 
// ── Mistake 2: NBA in always_comb for intermediate ──────────────
always_comb begin
    mid <= a ^ b;   // ⚠ NBA in comb: mid hasn't updated when next line runs
    out <= mid | c;  // ⚠ reads OLD mid
end
 
// FIX: use blocking in always_comb
always_comb begin
    mid = a ^ b;    // mid updates immediately
    out = mid | c;  // uses NEW mid
end
 
 
// ── Mistake 3: using = for reset in always_ff ───────────────────
always_ff @(posedge clk) begin
    if (!rst_n) q = '0;   // ⚠ blocking reset — inconsistent with NBA data path
    else        q <= d;
end
 
// FIX: use <= for reset too
always_ff @(posedge clk) begin
    if (!rst_n) q <= '0;   // consistent NBA throughout
    else        q <= d;
end

// ── Why $display shows wrong value after posedge ─────────────────
always_ff @(posedge clk) q <= d;  // NBA: q updates in NBA region
 
initial begin
    forever begin
        @(posedge clk);
        // $display fires in ACTIVE region — BEFORE NBA updates q
        $display("$display: q=%h (may be old value)", q);   // ← sees q_old
 
        // $strobe fires in POSTPONED region — AFTER NBA updates q
        $strobe(" $strobe: q=%h (final correct value)", q);  // ← sees q_new
    end
end
 
// ── Expected Output (d=0x55, q was 0x00) ─────────────────────────
// $display: q=00  ← Active region: NBA not yet applied
// $strobe:  q=55  ← Postponed region: q updated by NBA
 
// ── Rule: Always use $strobe when printing flip-flop outputs.
// Use $display only for combinational values or testbench signals
// that are driven with blocking (=) assignments.

// Figure 2 — correct: both RHS sampled before either LHS updates
always_ff @(posedge clk) begin
  stage1 <= d;
  stage2 <= stage1;      // reads the PRE-EDGE stage1
end
 
// Figure 3 — wrong: stage1 updates immediately, stage2 reads the new value
always_ff @(posedge clk) begin
  stage1 = d;
  stage2 = stage1;       // reads the value assigned one line above
end

// ── CORRECT: 4-stage pipeline using non-blocking ─────────────────
module pipeline4_correct (
    input  logic       clk, rst_n,
    input  logic [7:0] d,
    output logic [7:0] q4
);
    logic [7:0] s1, s2, s3;
 
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            s1 <= '0; s2 <= '0; s3 <= '0; q4 <= '0;
        end else begin
            s1 <= d;   // RHS: d_old
            s2 <= s1;  // RHS: s1_old (= d from 1 cycle ago)
            s3 <= s2;  // RHS: s2_old (= d from 2 cycles ago)
            q4 <= s3;  // RHS: s3_old (= d from 3 cycles ago)
        end                // All LHS update simultaneously in NBA → 4-cycle latency
    end
endmodule
 
// ── WRONG: 4-stage pipeline using blocking — all collapse to 1 stage
module pipeline4_broken (
    input  logic       clk, rst_n,
    input  logic [7:0] d,
    output logic [7:0] q4
);
    logic [7:0] s1, s2, s3;
 
    always_ff @(posedge clk) begin
        s1 = d;    // s1 immediately = d (new value)
        s2 = s1;   // s2 immediately = d (new s1) — 1 cycle latency GONE
        s3 = s2;   // s3 immediately = d (new s2) — 2 cycle latency GONE
        q4 = s3;   // q4 immediately = d (new s3) — 3 cycle latency GONE
    end            // Synthesis: q4 = d with 1 clock latency only (synthesis is right)
                   // Simulation: q4 = d with 1 clock latency (looks the same!)
                   // But: the INTERMEDIATE stages s1, s2, s3 are wrong in simulation
endmodule
 
// ── Test: verify the 4-cycle latency ─────────────────────────────
module tb;
    logic clk=0, rst_n;
    logic [7:0] d, q4_correct, q4_broken;
 
    always #5 clk = ~clk;
 
    pipeline4_correct u_c(.clk,.rst_n,.d,.q4(q4_correct));
    pipeline4_broken  u_b(.clk,.rst_n,.d,.q4(q4_broken));
 
    initial begin
        rst_n = 0; d = 8'h00;
        repeat(3) @(posedge clk); rst_n = 1;
        @(posedge clk); d = 8'hAA;   // push 0xAA into pipeline
        repeat(6) @(posedge clk);
        $strobe("correct: %h  broken: %h", q4_correct, q4_broken);
        // correct: appears at q4 after 4 cycles
        // broken: appears at q4 after 1 cycle
        $finish;
    end
endmodule

// ── Rule 1: Use = in initial blocks for immediate signal driving ──
initial begin
    rst_n = 0;   // ✅ drives rst_n=0 IMMEDIATELY at T=0
    data  = 8'hAA;
    @(posedge clk);
    rst_n = 1;   // ✅ drives rst_n=1 immediately after posedge
end
 
// ── Wrong: <= in initial block — signal changes in NBA region ────
initial begin
    data <= 8'hAA;   // ❌ NBA: data doesn't change until NBA region
    @(posedge clk);   // @(posedge clk) might fire BEFORE data updates!
    check(data);       // might check old data value
end
 
 
// ── Rule 2: Use $strobe to print flip-flop outputs ───────────────
initial begin
    forever begin
        @(posedge clk);
        $display("q=%h", q);   // ❌ Active region — q still old value!
        $strobe( "q=%h", q);   // ✅ Postponed region — q has new value
    end
end
 
 
// ── Rule 3: For clocking-block driven signals — use <= via cb ────
clocking drv_cb @(posedge clk);
    output #1 valid, data;   // output skew: drives 1ns after posedge
endclocking
 
initial begin
    @(drv_cb);
    drv_cb.data <= 8'hBB;   // ✅ clocking block assignment: use <=
    drv_cb.valid <= 1'b1;    // drives 1ns after next posedge
end
 
 
// ── Rule 4: Checking outputs — sample in Reactive region ─────────
clocking mon_cb @(posedge clk);
    input #-1 data_out, valid_out;  // input skew: samples 1ns before posedge
endclocking
// Clocking block input samples are BEFORE the clock edge — setup time
// This is why UVM monitors use clocking blocks for accurate timing

// ── Race Type 1: Two always_ff blocks writing same signal with = ──
always_ff @(posedge clk) shared = a;   // block 1
always_ff @(posedge clk) result = shared; // block 2 — sees new or old shared?
// VCS runs block 1 first: result = a (looks correct)
// Questa runs block 2 first: result = shared_old (different answer!)
// Synthesis: two flip-flops — result always gets shared_old (correct HW)
// ✅ Fix: use <= in both blocks
 
// ── Race Type 2: Read-after-Write in same always_ff block with = ─
always_ff @(posedge clk) begin
    stage1 = d;       // writes stage1 = d (new value)
    stage2 = stage1;  // reads NEW stage1 → stage2 = d (wrong — should be old)
end
// This is NOT a race between processes — it's sequential in one block.
// It's deterministic but wrong: both get d in same cycle.
// ✅ Fix: use <= for both
 
// ── Race Type 3: = and <= mixed in same block (non-deterministic) ─
always_ff @(posedge clk) begin
    tmp    =  a + b;    // blocking: tmp = a+b immediately (Active)
    result <= tmp;       // NBA: which tmp? pre-blocking (Active) or post?
end
// IEEE says: the value of tmp seen by <= is IMPLEMENTATION-DEFINED.
// VCS may give tmp_new, Questa may give tmp_old. Both are "correct" per spec.
// ✅ Fix: use automatic local variable for intermediate, then <=
always_ff @(posedge clk) begin
    automatic logic [8:0] tmp = a + b;  // local var: no net/reg — no NBA
    result <= tmp[7:0];                   // ✅ result gets tmp from this cycle
end
 
// ── Verification: detect blocking races with assertions ───────────
always_ff @(posedge clk) begin
    // XMR check: assert that result matches EXPECTED pre-clock value
    assert (result === $past(shared)) else
        $error("result=%h expected=%h — blocking race!", result, $past(shared));
end

// ❌ BUG: intended 2-stage pipeline with 2-cycle latency
always_ff @(posedge clk) begin
    stage1 = data_in;   // stage1 immediately = data_in (new)
    stage2 = stage1;    // stage2 immediately = data_in (new stage1!)
end
// Result: stage2 = data_in with 1-cycle latency, NOT 2-cycle
// Simulation: both stages have identical value every cycle
// Synthesis: correctly infers 2 FFs, data arrives at stage2 1 cycle late
// Impact: filter/DSP algorithm sees wrong delayed data → incorrect output
 
// ✅ FIX: use non-blocking — both stages capture pre-edge values
always_ff @(posedge clk) begin
    stage1 <= data_in;   // RHS: data_in_old (pre-edge)
    stage2 <= stage1;    // RHS: stage1_old (pre-edge) → 2-cycle latency ✅
end

// ❌ BUG: NBA in always_comb — mid is not updated when 'out' is assigned
always_comb begin
    mid <= a ^ b;     // schedules mid update for NBA region
    out <= mid | c;   // ❌ uses OLD mid (before this always_comb ran)
                      // out = (mid_old | c) — wrong!
end
// Simulation: out is 1 delta cycle behind its correct value
// The always_comb re-triggers (NBA updates mid) → out eventually correct
// But in between there's a glitch where out has wrong value
// Tool warning: "non-blocking assignment in always_comb" — treat as error
 
// ✅ FIX: use blocking = for all intermediate values in always_comb
always_comb begin
    mid = a ^ b;     // mid updated immediately
    out = mid | c;   // uses NEW mid — correct single-cycle behavior
end

// ❌ BUG: mixing = and <= in same always_ff
always_ff @(posedge clk) begin
    tmp    =  a + b;     // blocking: tmp updates immediately (Active region)
    result <= tmp;        // NBA: which tmp? IEEE says IMPLEMENTATION-DEFINED
    status <= (tmp[8]);   // IEEE says IMPLEMENTATION-DEFINED
end
// VCS interpretation:  result = new tmp (a+b from this cycle)
// Questa interpretation: result = old tmp (0 on first cycle)
// Both are "correct" per IEEE 1800. Your code is ambiguous.
// Will cause regressions to differ between tool vendors.
 
// ✅ FIX: Use local automatic variable for intermediate, then <=
always_ff @(posedge clk) begin
    automatic logic [8:0] tmp_local = a + b;  // local — no NBA semantics
    result <= tmp_local[7:0];                   // ✅ deterministic
    status <= tmp_local[8];                    // ✅ deterministic
end

// ❌ BUG: shift register split across two always_ff blocks
always_ff @(posedge clk) a = d_in;  // block 1: a = d_in (blocking)
always_ff @(posedge clk) b = a;    // block 2: b = a (but which a?)
 
// Scenario A: Simulator runs block 1 first
// a gets d_in (new). Then block 2: b = a = d_in (new). Result: b = d_in
// This makes b act like a wire to d_in, not a 1-cycle delayed register.
 
// Scenario B: Simulator runs block 2 first
// b = a (old). Then block 1: a = d_in. Result: b = a_old (correct FF behavior)
 
// Synthesis: always scenario B (b = a_old — two FFs in series)
// Simulation: depends on simulator. This is the classic sim/synth mismatch.
 
// ✅ FIX: use non-blocking — deterministic, matches synthesis
always_ff @(posedge clk) a <= d_in;  // RHS: d_in_old captured
always_ff @(posedge clk) b <= a;    // RHS: a_old captured. NBA updates: a=d_in, b=a_old

// ❌ BUG: = for reset path, <= for data path — inconsistent
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q =  '0;   // ❌ blocking reset
    else        q <= d;    // NBA data
end
// Lint: "Mixed blocking and non-blocking assignments in always_ff"
// IEEE: behavior when = and <= are mixed is implementation-defined
// VCS may simulate correctly; Questa may show glitches during reset
 
// ✅ FIX: use <= consistently for BOTH reset and data paths
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;   // ✅ consistent NBA
    else        q <= d;    // ✅ consistent NBA
end
// Rule: every assignment in an always_ff block must use <=. Always.

// ❌ BUG: $display fires in Active region — before NBA updates FF output
always_ff @(posedge clk) q <= d;
 
initial begin
    d = 8'hAA; #10;  // d=0xAA, posedge at T=5
    @(posedge clk);
    $display("q = %h", q);  // ❌ prints 0x00 (old value!) — Active region
    $strobe( "q = %h", q);  // ✅ prints 0xAA (new value)  — Postponed region
end
 
// ── Common engineer mistake that leads to wrong conclusions ───────
// Engineer sees $display showing 0x00 instead of 0xAA
// Thinks: "FF not working, d not being captured"
// Spends hours looking for a sensitivity list bug
// Reality: FF works fine, $display just fires before NBA
 
// ✅ RULE: Use $strobe for all debug prints involving FF outputs
// Use $display only for combinational signals driven with =

// ❌ BUG: <= in initial block — data not ready when @(posedge clk) fires
initial begin
    data  <= 8'hAA;   // NBA: scheduled for NBA region
    valid <= 1'b1;    // NBA: scheduled for NBA region
    @(posedge clk);   // fires in Active region
                      // ← But NBAs haven't committed yet!
    // DUT samples data and valid BEFORE they update
    // DUT sees old values: data=0x00, valid=0
    // Transaction appears to not be driven
end
 
// ✅ FIX: use = in initial blocks for immediate signal driving
initial begin
    data  = 8'hAA;   // ✅ immediate — data=0xAA right now
    valid = 1'b1;    // ✅ immediate
    @(posedge clk);   // DUT samples correct values
end

// ❌ BUG: swap with blocking — classic value-destruction bug
always_ff @(posedge clk) begin
    if (swap_en) begin
        a = b;   // a = b (new). Old a is LOST forever.
        b = a;   // b = a = b (already overwritten!)
                  // Both a and b now hold b_old. Swap failed.
    end
end
 
// ✅ FIX 1: non-blocking — RHS captured before any LHS updates
always_ff @(posedge clk) begin
    if (swap_en) begin
        a <= b;   // RHS: b_old captured
        b <= a;   // RHS: a_old captured
                  // NBA: a ← b_old, b ← a_old simultaneously. Swap works. ✅
    end
end
 
// ✅ FIX 2: if you must use blocking, need temp variable
always_ff @(posedge clk) begin
    if (swap_en) begin
        automatic logic [7:0] tmp = a;   // save a before overwriting
        a = b;
        b = tmp;   // restore old a from tmp. But still risky — use <=
    end
end
 
// KEY INSIGHT: This is THE canonical example of why <= exists.
// Hardware registers naturally swap — each FF captures its D input
// at the clock edge simultaneously. <= models this perfectly.