if-else & Unique/Priority Modifiers

// ── Form 1: simple if ─────────────────────────────────────────────
always_comb begin
    out = data;                // default
    if (enable) out = data_in; // override when enable=1
end
 
 
// ── Form 2: if-else ───────────────────────────────────────────────
always_comb begin
    if (sel)
        y = a;
    else
        y = b;      // 2-to-1 mux — every path assigns y
end
 
 
// ── Form 3: if-else if-else chain (priority mux) ─────────────────
always_comb begin
    out = '0;               // default: prevents latch
    if      (req[0]) out = data_a;  // highest priority
    else if (req[1]) out = data_b;
    else if (req[2]) out = data_c;
    else             out = data_d;  // lowest priority
end
// If req[0] and req[2] are both 1, req[0] wins — implicit priority
 
 
// ── Form 4: nested if ─────────────────────────────────────────────
always_comb begin
    result = '0;
    if (valid) begin
        if (write)  result = write_data;
        else        result = read_data;
    end
end

// ── unique if: conditions are mutually exclusive ──────────────────
always_comb begin
    out = '0;
    unique if (mode == 2'b00)  out = a + b;
    else if  (mode == 2'b01)  out = a - b;
    else if  (mode == 2'b10)  out = a & b;
    else                       out = a | b;
end
// Tool knows: only one condition is ever true at a time
// → Generates parallel mux, not priority chain
// → Simulator: warns if mode matches more than one branch (impossible here, but checked)
 
 
// ── unique if: simulation warning demonstration ───────────────────
always_comb begin
    out = '0;
    unique if (a && !b)  out = 8'hAA;
    else if  (!a && b)  out = 8'hBB;
    else if  (!a && !b) out = 8'h00;
    // What if a=1 and b=1? No branch matches!
    // → Simulator issues a WARNING: "unique if: no condition is true"
    // This is a design bug that plain if would SILENTLY ignore
end
 
 
// ── unique inside always_ff: use unique0, or plain if ─────────────
// ✗ WRONG. Whenever rst_n is high and en is low - the normal idle
//   condition of most flops - NO branch is taken, and unique if
//   reports a no-match violation. Every cycle. In every test.
//     unique if (!rst_n) q <= '0;
//     else if  (en)      q <= d;
//
// ✓ unique0 checks exclusivity but does NOT require a branch to be
//   taken, which is exactly the semantics an incomplete chain wants.
always_ff @(posedge clk) begin
    unique0 if (!rst_n)  q <= '0;
    else if   (en)       q <= d;
end
// ✓ plain if is also perfectly correct here: the priority is
//   intentional and there is nothing to check.

// ── priority if: overlapping conditions OK — first wins ───────────
always_comb begin
    irq_id = 3'b000;
    priority if (irq[0]) irq_id = 3'd0;  // IRQ0 has highest priority
    else if     (irq[1]) irq_id = 3'd1;
    else if     (irq[2]) irq_id = 3'd2;
    else if     (irq[3]) irq_id = 3'd3;
    else if     (irq[4]) irq_id = 3'd4;
end
// irq[0] and irq[3] both asserted → irq_id = 0 (intentional, no warning)
// No interrupts asserted         → simulator WARNS: "no priority if branch taken"
 
 
// ── priority if vs plain if — what changes? ───────────────────────
// Plain if:    • No simulation checks. Tool generates priority chain anyway.
// priority if: • Simulator warns if no branch matches (helps catch unhandled states)
//              • Tool KNOWS priority is intentional → may optimise encode logic
// unique if:   • Simulator warns if overlap OR no-match (strictest checking)
//              • Tool generates parallel mux (no priority chain needed)
// unique0 if:  • Warns on overlap, but NOT on no-match
//              • For conditions that are exclusive but deliberately
//                incomplete — the usual fix for reset-window X warnings

// ════ Example 1: plain if — for simple sequential decisions ═══════
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        state <= IDLE;
    else if (start)
        state <= BUSY;
    else if (done)
        state <= DONE;
    else
        state <= state;
end
// Plain if is fine here: rst_n, start, done are designed to not overlap
// See /learnings/systemverilog/procedural-blocks for always_ff vs always_comb
 
 
// ════ Example 2: unique if — ALU opcode decode (one-hot) ══════════
always_comb begin
    alu_out = '0;
    unique if (op == 4'h0) alu_out = a + b;     // ADD
    else if  (op == 4'h1) alu_out = a - b;     // SUB
    else if  (op == 4'h2) alu_out = a & b;     // AND
    else if  (op == 4'h3) alu_out = a | b;     // OR
    else if  (op == 4'h4) alu_out = a ^ b;     // XOR
    else if  (op == 4'h5) alu_out = ~a;       // NOT
    else if  (op == 4'h6) alu_out = a << 1;   // SHL
    else if  (op == 4'h7) alu_out = a >> 1;   // SHR
end
// op is a 4-bit field — only one opcode is ever encoded at a time
// unique if: warns if somehow two ops match, warns if op=8..15 (unhandled)
// synthesis: generates parallel logic, not a chain of 8 muxes
 
 
// ════ Example 3: priority if — interrupt controller ════════════════
always_comb begin
    irq_vec = 8'h00;
    irq_num = 3'd0;
    priority if (irq[7]) begin irq_vec[7] = 1; irq_num = 7; end
    else if     (irq[6]) begin irq_vec[6] = 1; irq_num = 6; end
    else if     (irq[5]) begin irq_vec[5] = 1; irq_num = 5; end
    else if     (irq[4]) begin irq_vec[4] = 1; irq_num = 4; end
    else if     (irq[3]) begin irq_vec[3] = 1; irq_num = 3; end
    else if     (irq[2]) begin irq_vec[2] = 1; irq_num = 2; end
    else if     (irq[1]) begin irq_vec[1] = 1; irq_num = 1; end
    else if     (irq[0]) begin irq_vec[0] = 1; irq_num = 0; end
end
// Multiple IRQs pending simultaneously is EXPECTED — priority if is correct
// Simulator: no overlap warning (intentional), warns if irq == 0 (nothing pending)

// ── Template 1: async reset only ─────────────────────────────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;
    else        q <= d;
end
 
 
// ── Template 2: async reset + synchronous enable ──────────────────
always_ff @(posedge clk or negedge rst_n) begin
    if      (!rst_n) q <= '0;    // async reset — highest priority
    else if (en)     q <= d;     // sync load when enabled
    // else: q holds its value (no assignment = hold)
end
 
 
// ── Template 3: async reset + sync load + sync clear ─────────────
always_ff @(posedge clk or negedge rst_n) begin
    if      (!rst_n) q <= '0;    // async reset
    else if (clr)    q <= '0;    // sync clear (higher priority than load)
    else if (load)   q <= d;     // sync load
    // else: hold
end
 
 
// ── Template 4: shift register with if ───────────────────────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        shreg <= 8'h00;
    else
        shreg <= {shreg[6:0], serial_in};  // shift left, new bit enters from right
end

// ════ MISTAKE 1: Missing default in always_comb — infers latch ═══
always_comb begin
    if (sel == 2'b00) out = a;   // ❌ what about sel = 2'b01, 10, 11?
    else if (sel == 2'b01) out = b;  // tool errors: latch inferred for 'out'
end
// ✅ FIX: add default or final else
always_comb begin
    out = '0;                        // default
    if      (sel == 2'b00) out = a;
    else if (sel == 2'b01) out = b;
end
 
 
// ════ MISTAKE 2: Confusing unique if and priority if ══════════════
// IRQ arbiter — conditions CAN overlap (multiple IRQs at once)
always_comb begin
    unique if (irq[0]) id = 0;   // ❌ unique if for IRQs that can overlap!
    else if   (irq[1]) id = 1;   // Simulator will warn every clock cycle
end
// ✅ FIX: use priority if when overlap is intentional
always_comb begin
    priority if (irq[0]) id = 0;  // overlap OK — no warning
    else if     (irq[1]) id = 1;
end
 
 
// ════ MISTAKE 3: Using = instead of <= in always_ff ══════════════
always_ff @(posedge clk) begin
    if (en) q = d;   // ❌ blocking in always_ff → covered in 5.6
end
// ✅ FIX: always use non-blocking inside always_ff
always_ff @(posedge clk) begin
    if (en) q <= d;  // ✅ correct
end

// ── Combinational if (always_comb) ────────────────────────────
always_comb begin
    out = '0;               // ALWAYS add default first!
    if      (cond_a) out = a;
    else if (cond_b) out = b;
    else             out = c;
end
 
// ── unique if: mutually exclusive, both overlap and no-match warned
always_comb begin
    out = '0;
    unique if  (op==2'b00) out = a;  // one-hot / enum decode
    else if (op==2'b01) out = b;
    else if (op==2'b10) out = c;
    else                out = d;
end
 
// ── priority if: overlap OK, warns on no-match ─────────────────
always_comb begin
    id = '0;
    priority if (req[0]) id = 0;   // interrupt / priority encoder
    else if     (req[1]) id = 1;
    else if     (req[2]) id = 2;
end
 
// ── Sequential if (always_ff) ─────────────────────────────────
always_ff @(posedge clk or negedge rst_n) begin
    if      (!rst_n) q <= '0;   // async reset
    else if (en)     q <= d;    // sync load
    // else: hold (no assignment = correct register hold)
end
 
// ── Decision guide ────────────────────────────────────────────
// Conditions mutually exclusive + must match?  → unique if
// Conditions can overlap, priority needed?     → priority if
// No special checking needed?                  → plain if
// Always add default assignment in always_comb!

// ── Testbench: proves unique if catches overlap, priority if doesn't ─
module tb_modifier_check;
    logic [3:0] req;
    logic [7:0] out_unique, out_priority;
 
    // DUT A: unique if — should warn when req[0] && req[1] both high
    always_comb begin
        out_unique = 8'h00;
        unique if (req[0]) out_unique = 8'hAA;
        else if  (req[1]) out_unique = 8'hBB;
        else if  (req[2]) out_unique = 8'hCC;
        else if  (req[3]) out_unique = 8'hDD;
    end
 
    // DUT B: priority if — no warning on overlap, intentional
    always_comb begin
        out_priority = 8'h00;
        priority if (req[0]) out_priority = 8'hAA;
        else if     (req[1]) out_priority = 8'hBB;
        else if     (req[2]) out_priority = 8'hCC;
        else if     (req[3]) out_priority = 8'hDD;
    end
 
    initial begin
        req = 4'b0000; #10;   // no requests — unique if warns (no match)
        req = 4'b0001; #10;   // req[0] only — clean, no warning
        req = 4'b0011; #10;   // req[0] AND req[1] — unique if WARNS, priority if silent
        req = 4'b0110; #10;   // req[1] AND req[2] — unique if WARNS, priority gives BB
        req = 4'b1000; #10;   // req[3] only — clean
        $display("out_unique=%h out_priority=%h", out_unique, out_priority);
        $finish;
    end
endmodule
 
// ── Expected Simulation Output ─────────────────────────────────────
// WARNING: unique if violation — all conditions are false (at req=0000)
// WARNING: unique if violation — multiple conditions are true (at req=0011)
// WARNING: unique if violation — multiple conditions are true (at req=0110)
// out_unique=dd out_priority=dd  (final state: req=1000, no overlap)

// ── Scenario: 4-input mux, one-hot select ─────────────────────────
// The spec says only one of {s0,s1,s2,s3} is ever high at a time.
 
// Form A: plain if — synthesis generates 3 chained muxes
always_comb begin
    out = '0;
    if      (s0) out = a;   // mux1: sel=s0
    else if (s1) out = b;   // mux2: sel=s1 (output of mux1 is one input)
    else if (s2) out = c;   // mux3: sel=s2 (output of mux2 is one input)
    else if (s3) out = d;   // mux4: sel=s3 (output of mux3 is one input)
end
// Synthesized: 3-level mux chain. s0 must propagate through ALL 3 muxes.
// Critical path: ~3 × mux_delay ≈ 750ps in 28nm
 
// Form B: unique if — synthesis generates parallel mux
always_comb begin
    out = '0;
    unique if (s0) out = a;   // Tool knows: only one can be true
    else if  (s1) out = b;   // → generates 4:1 one-hot mux
    else if  (s2) out = c;   // → ALL inputs evaluated in parallel
    else if  (s3) out = d;   // → 1-level mux
end
// Synthesized: 1-level parallel mux. ~250ps. 3× timing improvement.
// Bonus: simulator warns if two selects are high (spec violation caught)
 
// Form C: for truly overlapping signals, use priority if
always_comb begin
    out = '0;
    priority if (req[3]) out = d;  // highest priority
    else if     (req[2]) out = c;
    else if     (req[1]) out = b;
    else if     (req[0]) out = a;  // lowest priority
end
// Synthesized: priority encoder (4→2 binary) driving mux select
// ~log2(4) = 2 levels. Better than plain if chain.

// ── AXI-Lite slave address decoder ───────────────────────────────
// Address regions are mutually exclusive — unique if is correct
module axi_lite_decoder #(
    parameter logic [31:0] CTRL_BASE  = 32'h0000_0000,
    parameter logic [31:0] DATA_BASE  = 32'h0001_0000,
    parameter logic [31:0] STAT_BASE  = 32'h0002_0000,
    parameter logic [31:0] REGION_MSK = 32'hFFFF_0000
) (
    input  logic [31:0] awaddr,
    output logic        ctrl_sel, data_sel, stat_sel, err_sel
);
    always_comb begin
        // Default: error — address hits no valid region
        {ctrl_sel, data_sel, stat_sel, err_sel} = 4'b0001;
 
        unique if ((awaddr & REGION_MSK) == CTRL_BASE) begin
            ctrl_sel = 1; err_sel = 0;
        end else if ((awaddr & REGION_MSK) == DATA_BASE) begin
            data_sel = 1; err_sel = 0;
        end else if ((awaddr & REGION_MSK) == STAT_BASE) begin
            stat_sel = 1; err_sel = 0;
        end
        // No else needed — default covers error case
        // unique if: simulation warns if two regions decode simultaneously
        // (would indicate a parametrization error)
    end
endmodule
 
// ── Verification: check decoder with directed test ─────────────────
module tb_decoder;
    logic [31:0] awaddr;
    logic        ctrl_sel, data_sel, stat_sel, err_sel;
 
    axi_lite_decoder u_dut (.awaddr,.ctrl_sel,.data_sel,.stat_sel,.err_sel);
 
    initial begin
        awaddr = 32'h0000_0004; #1;
        assert(ctrl_sel && !err_sel) else $error("CTRL decode fail");
 
        awaddr = 32'h0001_0020; #1;
        assert(data_sel && !err_sel) else $error("DATA decode fail");
 
        awaddr = 32'h0003_0000; #1;  // unknown region
        assert(err_sel)             else $error("ERR decode fail");
        $finish;
    end
endmodule

// ── Power state arbiter: multiple power events can occur simultaneously
// Critical system event (thermal) must always win over user request
typedef enum logic [1:0] {
    PWR_FULL   = 2'b00,
    PWR_REDUCE = 2'b01,
    PWR_SLEEP  = 2'b10,
    PWR_OFF    = 2'b11
} pwr_state_t;
 
module pwr_ctrl (
    input  logic thermal_alert,   // hardware thermal sensor — HIGHEST priority
    input  logic battery_low,     // battery monitor
    input  logic user_sleep_req,  // software request
    input  logic user_wake_req,   // software request
    output pwr_state_t pwr_cmd
);
    always_comb begin
        pwr_cmd = PWR_FULL;         // default: full power
 
        priority if (thermal_alert) begin
            pwr_cmd = PWR_SLEEP;   // thermal: always overrides everything
        end else if (battery_low) begin
            pwr_cmd = PWR_REDUCE;  // battery: overrides user, not thermal
        end else if (user_sleep_req && !user_wake_req) begin
            pwr_cmd = PWR_SLEEP;
        end else if (user_wake_req) begin
            pwr_cmd = PWR_FULL;
        end
        // thermal_alert + battery_low + user_sleep all asserted simultaneously:
        // priority if → thermal wins, pwr_cmd = SLEEP. No simulation warning.
        // This is intentional design — priority if is the correct modifier.
    end
endmodule

// ── ALU scoreboard: uses if-else to compute reference model output
module alu_scoreboard;
    logic [7:0] a, b, dut_result;
    logic [3:0] op;
    logic        valid;
    int          pass_cnt = 0, fail_cnt = 0;
 
    // Reference model: uses unique if — op values are mutually exclusive
    function automatic logic [8:0] alu_ref(
        input logic [7:0] a, b,
        input logic [3:0] op
    );
        unique if  (op == 4'h0) return {1'b0, a} + {1'b0, b};   // ADD
        else if    (op == 4'h1) return {1'b0, a} - {1'b0, b};   // SUB
        else if    (op == 4'h2) return {1'b0, a & b};           // AND
        else if    (op == 4'h3) return {1'b0, a | b};           // OR
        else if    (op == 4'h4) return {1'b0, a ^ b};           // XOR
        else if    (op == 4'h5) return {1'b0, ~a};             // NOT
        else                    return 9'h000;                  // unhandled
    endfunction
 
    // Scoreboard: sample DUT output, compare with reference
    always @(posedge valid) begin
        automatic logic [8:0] expected = alu_ref(a, b, op);
        if (dut_result === expected[7:0]) begin
            pass_cnt++;
        end else begin
            $error("FAIL: op=%0h a=%0h b=%0h got=%0h exp=%0h",
                    op, a, b, dut_result, expected[7:0]);
            fail_cnt++;
        end
    end
endmodule