Design for Testability tutorials & labs.
Design for Testability, from why manufacturing test exists to a full scan + compression + ATPG signoff. Beginner-to-advanced and production-test aware: understand fault models and testability, insert and verify scan, reason about ATPG controllability and observability, add MBIST/LBIST and boundary scan, and — most of all — learn to debug the coverage loss and scan-chain failures that decide whether silicon ships.
Tutorials
Learn Design for Testability from beginner to advanced through structured tutorials.
Labs
Practice Design for Testability using progressively challenging hands-on labs.
What Design for Testability is
Design for Test is the practice of adding structure to a chip so manufacturing defects can be found after fabrication. The central technique is scan: flip-flops are stitched into shift registers so a tester can load any state directly and read the result out, instead of trying to reach it through functional operation. Around that sit fault models that describe what a defect looks like electrically, ATPG tools that generate patterns to detect those faults, compression to keep test data and time affordable, and built-in self-test for memories and logic. JTAG provides the standard access port for all of it.
Why it exists
A design can be logically perfect and still arrive from the fab with a shorted via or a transistor that switches too slowly. Those are physical defects, not design bugs, and every die must be screened for them individually. Without scan, reaching a specific internal state might take thousands of functional cycles, and observing the result might be impossible — so test cost and escape rate would both be unacceptable. DFT exists to make that screening tractable, and its quality shows up directly as defective parts per million shipped.
The part engineers get wrong
Functional verification and manufacturing test answer different questions, and conflating them is the most common conceptual error. Verification asks whether the design implements the intended function; test asks whether a specific manufactured die is free of physical defects. Their coverage metrics are not comparable either — code coverage and functional coverage measure how thoroughly the design intent was exercised, while fault coverage measures the fraction of modelled physical faults a pattern set can detect. A design can have complete functional coverage and poor fault coverage, and vice versa. Scan's contribution is to convert a hard sequential controllability and observability problem into one ATPG can attack far more like combinational logic.
Before you start
- Digital logic and flip-flop behaviour
- Basic RTL design and an idea of what synthesis produces
- Helpful: awareness of the physical implementation flow
What you will be able to do
- Explain what scan does and why it changes the test problem
- Distinguish stuck-at from transition faults, and say when each matters
- Reason about controllability and observability at a fault site
- Explain how ATPG generates and justifies a pattern
- Describe why compression is needed and what it trades away
- Explain where MBIST and LBIST fit alongside external ATPG
The learning path
- Why manufacturing test existsPhysical defects versus design bugs
- Fault modelsStuck-at, transition and what each represents electrically
- ScanTurning flip-flops into shift registers for direct state access
- Controllability and observabilityThe two properties ATPG depends on
- ATPGGenerating patterns and measuring fault coverage
- CompressionKeeping test data volume and tester time affordable
- Built-in self-testMBIST for memories, LBIST for logic
- JTAGThe standard access port for test and board-level interconnect
Core concepts
New to Design for Testability? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.