Learnings · PCIe

PCIe tutorials & labs.

The most complete PCI Express curriculum on the internet — from first principles (why shared buses stopped scaling, why switched serial fabrics won) before lanes and speeds, then through the layered architecture, enumeration, configuration space, BARs, TLPs, DLLPs, flow control, the physical layer and LTSSM, interrupts, DMA, switches, performance, RTL design, verification, debugging, system integration, and interview mastery.

Structured curriculum

Tutorials

Learn PCIe from beginner to advanced through structured tutorials.

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Hands-on practice

Labs

Practice PCIe using progressively challenging hands-on labs.

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What PCIe is

PCI Express is a layered, packet-based, point-to-point link. A device does not sit on a shared bus — it has its own serial link to a switch or root complex, and every access becomes a packet. The Transaction Layer builds TLPs carrying reads, writes and completions; the Data Link Layer adds sequence numbers, CRC and an ACK/NAK replay scheme so a corrupted packet is retransmitted without the transaction layer knowing; the Physical Layer trains the link and moves symbols. On top of that sits configuration space and enumeration, which is how a system discovers devices and assigns them address windows through BARs.

Why it exists

Parallel buses stopped scaling: every added device loaded the bus, skew limited frequency, and one slow participant held everyone up. Serialising each link and giving every device its own point-to-point connection removed both the electrical and the arbitration ceiling. Layering then let each concern be solved once — reliability at the link layer, routing and ordering at the transaction layer — which is why the same architecture has carried through many generations of speed increases without the software model changing.

The part engineers get wrong

PCIe flow control is receiver-buffer accounting, not congestion control. A credit does not mean the fabric is busy; it means the receiver has advertised how much buffer space it has for a specific packet category — posted, non-posted or completion, header and data counted separately. A transmitter that runs out of credits stops because the far end has nowhere to put the packet, so a stall is a buffer question, not a bandwidth one. The second thing worth knowing early is that reliability is split by layer: the Data Link Layer replays a corrupted packet from its replay buffer, and the Transaction Layer never learns it happened.

Before you start

Digital logic and clocked design
Basic packet/protocol concepts — headers, payloads, sequence numbers
Helpful: familiarity with memory-mapped register access

What you will be able to do

Identify a TLP's type and explain how it is routed to its destination
Explain what each layer contributes, and which layer recovers an error
Reason about credit exhaustion and why a transmitter has stopped
Follow enumeration: how a device is discovered and given address windows
Explain what BARs do and how a host reaches a device's registers
Describe the LTSSM states a link moves through while training

The learning path

Layered architectureWhy PCIe splits the job into transaction, link and physical layers
Transaction layerTLP types, headers and payloads
RoutingAddress, ID and implicit routing, and when each applies
CompletionsHow a non-posted request gets its answer back
Data link reliabilityDLLPs, sequence numbers, ACK/NAK and replay
Flow controlCredit accounting per traffic category
Configuration and enumerationDiscovering devices and assigning BAR windows
LTSSMLink training and the state machine that governs it
Ordering and debugWhat may pass what, and how to diagnose a stalled link

Core concepts

TLP packet typesThe transaction categories and what each is used for TLP headersHow a request encodes its target, size and attributes TLP routingAddress, ID and implicit routing through the hierarchy DLLP typesLink-layer packets that never reach the transaction layer Replay bufferHow a corrupted packet is retransmitted transparently Flow control creditsReceiver buffer accounting, per category and direction Completion handlingHow answers return, and what their status codes mean EnumerationHow the system discovers devices and builds the hierarchy BAR address assignmentGiving a device its address window in the memory map LTSSMThe link training state machine and the states it moves through

New to PCIe? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.

Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.

Follow the full curriculum

Where this leads

UCIeDie-to-die interconnect that borrows layering ideas and can transport protocol traffic between chiplets AMBA AXIThe on-chip interconnect PCIe traffic usually lands on once inside an SoC UVMThe methodology protocol testbenches and scoreboards are built with

Standards: PCI-SIG — The body that publishes the PCI Express base specification