Procedural Blocks

// ── Testbench: clock gen + reset + stimulus ─────────────────────
module tb;
    logic clk = 0;
    logic rst_n;
    logic [7:0] data;
 
    // ① Clock generator — runs forever via always
    always #5 clk = ~clk;   // 10-unit period
 
    // ② Reset + stimulus — runs once from T=0
    initial begin
        rst_n = 0; data = 8'h00;
        @(posedge clk); @(posedge clk);  // hold reset 2 cycles
        rst_n = 1;
        @(posedge clk); data = 8'hAA;
        @(posedge clk); data = 8'h55;
        @(posedge clk);
        $display("Simulation complete");
        $finish;
    end
 
    // ③ Memory pre-load — another initial block
    initial begin
        $readmemh("program.hex", u_dut.mem);  // backdoor load
    end
 
    // ④ Multiple initial blocks run CONCURRENTLY starting at T=0
    initial begin
        $dumpfile("sim.vcd");
        $dumpvars(0, tb);   // VCD waveform dump
    end
 
endmodule

// ❌ Legacy always — tool doesn't know your intent
always @(*) begin           // @(*) = manual auto-sensitivity
    y = a & b;             // intended: combinational — but tool can't verify
end
 
always @(posedge clk) begin  // intended: flip-flop — but tool can't verify
    q <= d;
end
 
// ✅ Modern SystemVerilog — intent is explicit and verified by the tool
always_comb begin
    y = a & b;             // tool GUARANTEES combinational, auto-sensitivity
end
 
always_ff @(posedge clk) begin  // tool GUARANTEES flip-flop inference
    q <= d;
end
 
// ── The sensitivity list bug that always hides ──────────────────
always @(a) begin            // ❌ b missing from list!
    y = a & b;             // simulation: y doesn't update when b changes
end                          // synthesis: works (uses all inputs)
                             // → sim/synth mismatch — impossible to debug
 
// always_comb would catch this immediately — no sensitivity list to get wrong

// ── Rule 1: No sensitivity list — it's automatic ─────────────────
always_comb begin
    y = a & b;    // auto-senses {a, b} — no @(*) needed or allowed
end
 
 
// ── Rule 2: Every output must be assigned on ALL paths ────────────
always_comb begin
    out = 4'h0;           // ← default assignment: prevents latch
    if (enable)
        out = data_in;    // overrides default when enable=1
end
 
 
// ── Rule 3: Functions are fine inside always_comb ─────────────────
function automatic logic [2:0] priority_enc(input logic [7:0] req);
    priority_enc = 3'b0;
    for(int i=7; i>=0; i--) if(req[i]) priority_enc = i[2:0];
endfunction
 
always_comb begin
    grant   = 8'h0;
    grant_id = priority_enc(request);  // function call in always_comb ✅
    if (|request)
        grant[grant_id] = 1;
end
 
 
// ── What always_comb CANNOT contain ──────────────────────────────
always_comb begin
    // @(posedge clk);    ← ILLEGAL — timing control in always_comb
    // #10;               ← ILLEGAL — delay in always_comb
    // wait(valid);       ← ILLEGAL — wait in always_comb
    y = a ^ b;         // ✅ pure combinational
end

// ── Pattern 1: Asynchronous active-low reset (most common in ASIC) ─
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= 8'h00;    // async reset: fires WITHOUT clock
    else        q <= d;
end
 
 
// ── Pattern 2: Synchronous reset (common in FPGA) ─────────────────
always_ff @(posedge clk) begin  // only posedge in sensitivity list
    if (!rst_n) q <= 8'h00;    // sync reset: fires WITH clock
    else        q <= d;
end
 
 
// ── Pattern 3: 8-bit counter with enable ────────────────────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)      count <= 8'h00;
    else if (en)    count <= count + 8'h01;
end
 
 
// ── Pattern 4: 3-state FSM ───────────────────────────────────────
typedef enum logic [1:0] {IDLE, BUSY, DONE} state_t;
state_t state, next_state;
 
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) state <= IDLE;
    else        state <= next_state;  // registers the NEXT state
end
 
always_comb begin   // next-state logic is COMBINATIONAL
    next_state = state;
    case (state)
        IDLE: if (start) next_state = BUSY;
        BUSY: if (done)  next_state = DONE;
        DONE:              next_state = IDLE;
    endcase
end
 
 
// ── Rule: always use <= (non-blocking) inside always_ff ──────────
always_ff @(posedge clk) begin
    q1 <= d;      // ✅ non-blocking: models a real register correctly
    // q1 = d;   ← ❌ blocking in always_ff: timing hazard (covered in 5.6)
end

// ── The Reset Synchronizer — industry standard for async reset ──
// Problem: Async reset deassertion can violate setup/hold on FF.
// Solution: Synchronize the deassertion to the clock domain.
module reset_sync #(parameter int STAGES = 2) (
    input  logic clk,
    input  logic rst_n_async,   // async from power-on or pin
    output logic rst_n_sync     // synchronized, safe to use
);
    logic [STAGES-1:0] sync_chain;
 
    always_ff @(posedge clk or negedge rst_n_async) begin
        if (!rst_n_async)
            sync_chain <= '0;       // async assert propagates immediately
        else
            sync_chain <= {sync_chain[STAGES-2:0], 1'b1};
    end
 
    assign rst_n_sync = sync_chain[STAGES-1];
    // Deassertion travels through N flip-flops — synchronized to clk.
    // All downstream FFs see clean synchronous deassertion.
endmodule
 
// ── 2-stage Pipeline using always_ff — waveform-correct model ───
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= '0;
        stage2 <= '0;
    end else begin
        stage1 <= data_in;   // RHS captured at clock edge (old value)
        stage2 <= stage1;    // RHS = old stage1 — correct 2-cycle latency
    end                       // LHS updates in NBA region after both evaluate
end

// ── Intentional latch: always_latch makes intent clear ─────────
always_latch begin
    if (enable)
        q = d;          // transparent when enable=1
                        // holds q when enable=0 (latch behaviour)
end
 
 
// ── Accidental latch from always_comb (common mistake) ──────────
always_comb begin
    if (enable)
        out = data;     // ❌ 'out' not assigned when enable=0
end                     // → tool ERRORS: "always_comb infers a latch"
                        // Fix: add default assignment at top
 
always_comb begin
    out = '0;          // ✅ default: no latch possible
    if (enable)
        out = data;
end
 
 
// ── When you might legitimately use always_latch ────────────────
// Specific bus protocols (some older standards) require transparent latches
// for address/data hold. Outside of that: always prefer always_comb or always_ff.

// ── Root Cause 1: if without else ────────────────────────────────
always_comb begin
    if (valid) data_out = fifo_data;  // ❌ what when valid=0? → latch
end
always_comb begin
    data_out = '0;                    // ✅ default → no latch
    if (valid) data_out = fifo_data;
end
 
// ── Root Cause 2: case missing default, one signal unassigned ────
always_comb begin
    case (opcode)
        2'b00: begin result = a + b; carry = 1'b0; end
        2'b01: begin result = a - b; end  // ❌ carry missing here → latch on carry
        default: begin result = '0; carry = 1'b0; end
    endcase
end
// ✅ Fix: assign carry at top, OR assign in every case arm
always_comb begin
    {carry, result} = '0;             // ✅ default: both covered
    case (opcode)
        2'b00: {carry, result} = a + b;
        2'b01: result = a - b;         // carry stays 0 from default
    endcase
end
 
// ── Root Cause 3: Nested if — inner branch misses assignment ─────
always_comb begin
    out = '0;                          // outer default: not enough!
    if (mode) begin
        if (enable) out = data;       // ✅ covered
        // mode=1, enable=0 → out not assigned here
        // BUT outer default covers it! Wait — does it?
        // YES — out='0 at top covers ALL paths including this one.
        // Lesson: one default at the TOP covers ALL nested paths.
    end
end

// ─────────────────────────────────────────────────────────────────────────────
//  Three decoders, same intent, three outcomes:
//    A: always_comb with an unassigned path  -> LATCH (holds the old value)
//    B: always_comb with a default assigned  -> pure combinational
//    C: always_latch                          -> a latch, but a DECLARED one
//
//  vcs -sverilog latch_proof.sv && ./simv   |   xrun -sv latch_proof.sv
// ─────────────────────────────────────────────────────────────────────────────
module latch_proof;
 
  timeunit 1ns; timeprecision 1ps;
 
  logic [1:0] sel;
  logic [3:0] out_latch, out_comb, out_declared;
  logic       en;
  int         errors = 0;
 
  // ── A: sel==3 assigns nothing, so out_latch must HOLD. That retention is
  //      the inferred latch - storage nobody asked for.
  always_comb begin
    case (sel)
      2'd0: out_latch = 4'h1;
      2'd1: out_latch = 4'h2;
      2'd2: out_latch = 4'h4;
      // 2'd3: no assignment  -> holds previous value
    endcase
  end
 
  // ── B: the fix. Assign a default FIRST, then let the case override it.
  //      Every path now writes out_comb, so nothing is retained.
  always_comb begin
    out_comb = 4'h0;                  // default - this line is the whole fix
    case (sel)
      2'd0: out_comb = 4'h1;
      2'd1: out_comb = 4'h2;
      2'd2: out_comb = 4'h4;
      default: ;                       // documented: default already applied
    endcase
  end
 
  // ── C: a latch on purpose. Same storage as A, but declared - so a reviewer
  //      and the linter both see a decision rather than an accident.
  always_latch
    if (en) out_declared <= {2'b00, sel};
 
  task automatic check(string label, logic [3:0] got, logic [3:0] exp);
    if (got !== exp) begin
      errors++;
      $display("  ** FAIL %-22s got 0x%0h, expected 0x%0h", label, got, exp);
    end else
      $display("     ok   %-22s 0x%0h", label, got);
  endtask
 
  initial begin
    en = 1'b0;
 
    sel = 2'd2; #1;
    check("sel=2 latch version",  out_latch, 4'h4);
    check("sel=2 comb version",   out_comb,  4'h4);
 
    // The moment of truth: move to the unassigned path.
    sel = 2'd3; #1;
    // A retains 0x4 - it is storing. B goes to its default - it is logic.
    check("sel=3 latch RETAINED", out_latch, 4'h4);   // proves the latch
    check("sel=3 comb defaulted", out_comb,  4'h0);   // proves no storage
 
    if (errors == 0)
      $display("\n  [PASS] the unassigned path retained its value - that retention IS the latch");
    else
      $display("\n  [FAIL] %0d check(s) failed", errors);
    $finish;
  end
 
endmodule

     ok   sel=2 latch version     0x4
     ok   sel=2 comb version      0x4
     ok   sel=3 latch RETAINED    0x4
     ok   sel=3 comb defaulted    0x0
 
  [PASS] the unassigned path retained its value - that retention IS the latch

// ════ MISTAKE 1: Putting combinational logic in always_ff ════════
always_ff @(posedge clk) begin
    y = a & b;   // ❌ combinational inside always_ff — adds unwanted register
end
// ✅ FIX: use always_comb for combinational logic
always_comb begin
    y = a & b;   // ✅ pure combinational — no register inferred
end
 
 
// ════ MISTAKE 2: Missing default in always_comb → latch ══════════
always_comb begin
    if (sel) out = a;   // ❌ what is 'out' when sel=0? → latch inferred → tool errors
end
// ✅ FIX: default assignment at the top
always_comb begin
    out = '0;          // ✅ default covers sel=0 path
    if (sel) out = a;
end
 
 
// ════ MISTAKE 3: Writing initial inside RTL (not testbench) ══════
module bad_rtl (...);
    initial q = 0;     // ❌ initial in RTL — synthesis ignores or errors
    // ✅ FIX: use reset in always_ff instead
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) q <= 0;   // ✅ synthesisable reset
        else        q <= d;
    end
endmodule
 
 
// ════ MISTAKE 4: Blocking assignment (=) inside always_ff ════════
always_ff @(posedge clk) begin
    q1 = d;    // ❌ blocking in always_ff — race condition (covered in 5.6)
    q2 = q1;   // q2 gets new q1 — behaviour differs from <= version!
end
// ✅ FIX: always use non-blocking (<=) in always_ff
always_ff @(posedge clk) begin
    q1 <= d;   // ✅ evaluates RHS at clock edge, updates after
    q2 <= q1;  // uses OLD q1 — models a 2-stage pipeline correctly
end

// ── initial: runs once, testbench only ────────────────────────
initial begin
    rst_n = 0; @(posedge clk); rst_n = 1;
    $finish;
end
 
// ── always: legacy — only use for clock gen ────────────────────
always #5 clk = ~clk;   // testbench clock generator
 
// ── always_comb: combinational RTL ────────────────────────────
always_comb begin
    out = '0;            // default first — prevents latches
    if (en) out = data;  // auto-sensitivity, no @(*) needed
end
 
// ── always_ff: sequential RTL ─────────────────────────────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;   // async reset
    else        q <= d;     // use <= (non-blocking)
end
 
// ── always_latch: intentional latch (rarely needed) ────────────
always_latch begin
    if (enable) q = d;    // transparent when enable=1
end
 
// ── Key rules ─────────────────────────────────────────────────
// always_comb:  no @, no #, always add a default assignment
// always_ff:    always use <= (non-blocking), include reset
// initial:      testbench only — never in RTL intended for synthesis
// always:       avoid — use always_comb or always_ff instead
// always_latch: avoid — almost always a design error

module delta_demo;
    logic clk = 0;
    logic [7:0] d, q, doubled;
 
    always #5 clk = ~clk;
 
    // Sequential: captures d on posedge clk
    always_ff @(posedge clk) q <= d;
 
    // Combinational: computes doubled from q
    always_comb doubled = q << 1;
 
    // ── What happens at posedge clk? ──────────────────────────────
    // T=5ns, Delta 0 (Active):   always_ff evaluates: RHS d is read (old d)
    // T=5ns, Delta 0 (NBA):      q gets new value (= old d)
    // T=5ns, Delta 1 (Active):   always_comb sees q changed → re-evaluates
    //                            doubled = q << 1 (uses new q)
    // T=5ns, Delta 1 (Postponed):$strobe shows final stable doubled value
    // ─────────────────────────────────────────────────────────────
    // $display at posedge might show OLD doubled (Delta 0).
    // $strobe at posedge shows NEW doubled (Postponed — final stable).
    // This is why verification engineers use $strobe not $display for FF outputs!
 
    initial begin
        d = 8'h0A;
        @(posedge clk);
        $display("$display: q=%0h doubled=%0h", q, doubled);  // may show stale
        $strobe ("$strobe:  q=%0h doubled=%0h", q, doubled);  // shows final
        $finish;
    end
endmodule
 
// ── Expected Output ───────────────────────────────────────────────
// $display: q=0a doubled=00   ← caught between Delta 0 and Delta 1
// $strobe:  q=0a doubled=14   ← after Delta 1 settles (0x0A<<1=0x14)

module tb_fifo;
    // ── Signals ───────────────────────────────────────────────────
    logic       clk, rst_n;
    logic       wr_en, rd_en;
    logic [7:0] wr_data, rd_data;
    logic       full, empty;
    int         error_count = 0;
 
    // ── DUT instantiation ────────────────────────────────────────
    fifo_8x16 u_dut (.clk,.rst_n,.wr_en,.rd_en,.wr_data,.rd_data,.full,.empty);
 
    // ── ① Clock generator: always (only legitimate use) ─────────
    always #5 clk = ~clk;
 
    // ── ② Reset generator: initial (runs once at T=0) ────────────
    initial begin
        clk = 0; rst_n = 0; wr_en = 0; rd_en = 0;
        repeat(4) @(posedge clk);
        rst_n = 1;
    end
 
    // ── ③ Stimulus driver: initial with task calls ───────────────
    initial begin
        @(posedge rst_n);                // wait for reset to deassert
        repeat(2) @(posedge clk);
        write_word(8'hA5);
        write_word(8'h3C);
        read_word();
        read_word();
        repeat(2) @(posedge clk);
        $display("Errors: %0d", error_count);
        $finish;
    end
 
    // ── ④ Monitor + scoreboard: always (edge-triggered sampling) ─
    logic [7:0] ref_queue[$];
    always @(posedge clk) begin
        if (wr_en && !full)  ref_queue.push_back(wr_data);
        if (rd_en && !empty) begin
            automatic logic [7:0] exp = ref_queue.pop_front();
            if (rd_data !== exp) begin
                $error("MISMATCH: got %0h exp %0h", rd_data, exp);
                error_count++;
            end
        end
    end
 
    // ── ⑤ Combinational assertion: always_comb ───────────────────
    always_comb begin
        assert (!(full && empty))       // FIFO can't be both full AND empty
            else $fatal(1, "FIFO state machine error!");
    end
 
    // ── ⑥ Watchdog: initial (fires once, kills runaway sim) ──────
    initial begin
        #100_000;
        $fatal(1, "Watchdog timeout — simulation stuck!");
    end
 
    // ── Tasks ─────────────────────────────────────────────────────
    task automatic write_word(input logic [7:0] data);
        @(posedge clk); wr_en = 1; wr_data = data;
        @(posedge clk); wr_en = 0;
    endtask
    task automatic read_word();
        @(posedge clk); rd_en = 1;
        @(posedge clk); rd_en = 0;
    endtask
endmodule

// ── This is NOT a race — this is correct combinational chaining ──
always_comb mid = a & b;         // Block 1
always_comb out = mid | c;       // Block 2 reads mid
 
// When a changes:
// Delta 0: Block 1 fires, mid updates
// Delta 1: Block 2 sees mid changed, fires, out updates
// Delta 2: Nothing changes → converges. Correct behavior.
// always_comb chains settle through delta cycles automatically.
 
// ── THIS is a race / oscillation ─────────────────────────────────
always_comb a = b ^ c;  // a depends on b
always_comb b = a & d;  // b depends on a — FEEDBACK LOOP!
 
// When b changes → a changes → b changes → a changes → ... forever
// Simulator detects delta cycle limit exceeded → error or X
// VCS: "Combinational loop detected"
// Questa: "Iteration limit exceeded"
// This produces X in simulation, oscillation in real silicon
 
// ── Identifying race conditions in waveform ───────────────────────
// Symptom 1: Signal toggles X within same timestamp
// Symptom 2: $display shows different value than waveform
// Symptom 3: Simulation gives different result on rerun with different seed
// Symptom 4: Two simulators give different RTL results on same testbench

// ── The Bug: incomplete sensitivity list in legacy always ─────────
module adder_bad (
    input  logic [7:0] a, b, c,
    output logic [8:0] sum
);
    always @(a, b) begin   // ❌ c missing from sensitivity list!
        sum = a + b + c;   // sim: sum only updates when a or b changes
    end                    // synth: sum correctly updates when c changes
endmodule
 
// ── Symptoms in simulation ────────────────────────────────────────
// At T=10: a=3, b=5, c=2 → sum=10 (a+b+c, a changed) ← correct
// At T=20: c=7 (only c changes) → sum stays 10! ← WRONG in sim
// At T=30: a=4 → sum=4+5+7=16 ← correct again (but c=7 now used)
// Synthesis netlist: sum always = a+b+c → different behavior!
 
// ── The Fix: always_comb — problem impossible ─────────────────────
module adder_good (
    input  logic [7:0] a, b, c,
    output logic [8:0] sum
);
    always_comb
        sum = a + b + c;   // auto-sensitivity: {a,b,c} — always correct
endmodule

// ── Pattern 1: Async Active-Low Reset (ASIC standard) ────────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;   // fires immediately when rst_n goes low
    else        q <= d;     // normal operation
end
// Synthesis: infers DFF with asynchronous active-low clear
// Timing: rst_n path constrained by async check (recovery, removal)
 
// ── Pattern 2: Sync Active-Low Reset (FPGA standard) ─────────────
always_ff @(posedge clk) begin
    if (!rst_n) q <= '0;   // fires at next posedge clk after rst_n low
    else        q <= d;
end
// Synthesis: infers DFF with synchronous reset — clean STA
// Concern: if clk stops, sync reset cannot clear the register
 
// ── Pattern 3: Async Assert, Sync Deassert (best of both) ────────
// Use a reset synchronizer (see always_ff section above) to produce
// rst_n_sync, then use it as async reset input — assertion is still
// immediate, but deassertion is synchronous to clock. This is the
// gold standard in ASIC methodology.
 
// ── Pattern 4: Reset with Set-able Default (not all 0) ───────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) state <= IDLE;    // reset to IDLE, not 0
    else        state <= next_state;
end
// Synthesis: infers DFF with preset/clear depending on tool
// Concern: some cells don't support non-zero reset — check lib
 
// ── Pattern 5: Conditional Reset (only some FFs reset) ───────────
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg  <= '0;     // control registers reset
        // data_pipe <= '0;   ← purposely NOT reset (saves area/power)
        // DFT tool: data_pipe path marked "no reset" in DFT constraints
    end else begin
        ctrl_reg  <= ctrl_next;
        data_pipe <= data_in;   // unreset FF — valid after 1st reset cycle
    end
end
// Area/power saving: not every FF needs reset in datapath
// Constraint: initialize in SW, or gate output with a valid signal

// ❌ BUG: c is not in the sensitivity list
always @(a or b) begin    // c is missing
    out = a & b & c;
end
 
// Simulation: 'out' only re-evaluates when a or b change.
// If c changes alone, out stays at its old value. Looks like a hold violation.
// Synthesis: synthesis reads ALL signals — out = a&b&c always correct.
// Chip behavior: correct. Simulation: wrong. Bug is invisible at tape-out.
 
// ✅ FIX: Replace always @(a or b) with always_comb
always_comb out = a & b & c;  // auto-sense: {a,b,c} — bug impossible

// ❌ INTENDED: 2-stage pipeline (data_in → stage1 → stage2)
always_ff @(posedge clk) begin
    stage1 = data_in;   // blocking: stage1 updates IMMEDIATELY
    stage2 = stage1;    // blocking: reads NEW stage1, not old stage1
end
// Result: stage2 = data_in at same clock edge → 1-stage pipeline, not 2
 
// ✅ FIX: Non-blocking — both RHS evaluated with OLD values first
always_ff @(posedge clk) begin
    stage1 <= data_in;  // RHS captured: data_in (old)
    stage2 <= stage1;   // RHS captured: old stage1
end                     // both update in NBA region simultaneously
// Result: stage2 = old stage1 = data_in from previous cycle → correct 2-stage

// ❌ BUG: always block with no timing control — infinite loop at T=0
always begin
    if (enable)
        counter = counter + 1;  // ← runs forever in zero time
end                              // ← simulator never advances time
 
// Symptom: simulation binary starts, prints nothing, hangs forever.
// CPU usage: 100% on one core. No VCD output.
// $finish is never reached. Kill with Ctrl+C.
 
// ❌ Also wrong: forever loop with no timing control
initial forever begin
    data = $random;   // infinite Active region loop
end
 
// ✅ FIX 1: Add timing control — yield simulation time
always @(posedge clk) begin
    if (enable) counter <= counter + 1;
end
 
// ✅ FIX 2: Add delay — yields time between iterations
initial forever begin
    @(posedge clk); data = $urandom_range(0, 255);
end

// ❌ BUG: case covers only opcodes 0,1,2 — what about 3?
always_comb begin
    case (opcode[1:0])
        2'b00: alu_out = a + b;
        2'b01: alu_out = a - b;
        2'b10: alu_out = a & b;
        // 2'b11: NOT HANDLED → alu_out holds last value → LATCH
    endcase
end
// always_comb tool ERROR: "Latch inferred on alu_out"
// Directed test: only tests 0,1,2 → passes
// Random test: eventually generates opcode=3 → stale alu_out
 
// ✅ FIX: Always add default assignment at top
always_comb begin
    alu_out = '0;         // ← default: covers ALL unhandled opcodes
    case (opcode[1:0])
        2'b00: alu_out = a + b;
        2'b01: alu_out = a - b;
        2'b10: alu_out = a & b;
        2'b11: alu_out = a | b;  // ← or: default handles it
    endcase
end

// ❌ BUG: Two always_ff blocks both drive 'q'
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;
    else        q <= channel_a_data;
end
 
always_ff @(posedge clk) begin
    if (override_en) q <= override_val;  // ❌ second driver of q!
end
 
// Symptom: q = X whenever both blocks try to write different values.
// Tool Warning: "Multiple drivers on net q"
// Synthesis: CRITICAL ERROR — cannot resolve multi-driven net
 
// ✅ FIX: Merge into single always_ff with explicit priority
always_ff @(posedge clk or negedge rst_n) begin
    if      (!rst_n)     q <= '0;
    else if (override_en) q <= override_val;   // override takes priority
    else                  q <= channel_a_data;  // normal operation
end

// ❌ BUG: rst is active-HIGH (testbench drives rst=1 to reset)
// But the module checks !rst — this is always false when rst=1!
always_ff @(posedge clk or posedge rst) begin
    if (!rst) q <= '0;   // ❌ !rst = !1 = 0 → reset condition is NEVER true
    else      q <= d;     // rst=1 → else branch → q gets d during reset!
end
 
// Simulation: q never initialises to 0. Stays X throughout.
// Waveform: rst pulse visible, q stays X, no response to reset.
 
// ✅ FIX: Match polarity — active-HIGH rst → if(rst), not if(!rst)
always_ff @(posedge clk or posedge rst) begin
    if (rst)  q <= '0;    // ✅ active-high: fires when rst=1
    else      q <= d;
end
 
// ─── Naming convention prevents this bug ─────────────────────────
// rst   → active high (fires when HIGH)  → check: if(rst)
// rst_n → active low  (fires when LOW)   → check: if(!rst_n)
// The _n suffix is an industry convention for active-low signals.
// Sensitivity: posedge rst (active-high) vs negedge rst_n (active-low)

// ❌ BUG: A task with timing control called from always_comb
task automatic sample_bus(output logic [7:0] val);
    @(posedge clk);    // ← timing control inside task
    val = data_bus;
endtask
 
always_comb begin
    sample_bus(captured);  // ❌ ERROR: always_comb cannot block on @
end
// Compiler: "Timing controls not allowed in always_comb"
 
// ✅ FIX: Use a function (functions cannot contain timing controls)
function automatic logic [7:0] process_bus(input logic [7:0] raw);
    return raw ^ 8'hFF;   // ✅ pure combinational — no timing
endfunction
 
always_comb begin
    processed = process_bus(data_bus);   // ✅ function call: legal
end
 
// For the original sampling intent: use always_ff
always_ff @(posedge clk) captured <= data_bus;  // correct

// ── Scenario: Gray-code counter output feeds combinational decode
// Gray-code: only 1 bit changes at a time — but NOT in simulation!
// In simulation, multiple bits appear to change "simultaneously"
// but they are actually staggered by gate delays in real silicon.
 
always_comb begin
    case (gray_count)          // gray_count = [2:0] changes 010→011
        3'b000: sector = 3'd0;  // In sim: appears atomic (same delta)
        3'b001: sector = 3'd1;  // In silicon: bit[1] and bit[0] may
        3'b011: sector = 3'd2;  // switch at slightly different times
        3'b010: sector = 3'd3;  // → illegal code 3'b010 momentarily
        default: sector = 3'd0; // → sector glitches to wrong value
    endcase
end
 
// Simulation: looks clean (atomic change)
// Silicon: glitches on sector during counter transitions
// Symptom in silicon: incorrect sector decode for 1-2 gate delays
 
// ✅ FIX: Register the output to filter glitches
always_ff @(posedge clk) sector_reg <= sector; // register filters glitch

// ❌ BUG: sel starts as X in simulation (undriven at T=0)
always_comb begin
    case (sel)
        2'b00: mux_out = in_a;
        2'b01: mux_out = in_b;
        2'b10: mux_out = in_c;
        2'b11: mux_out = in_d;
        // No default: if sel=2'bXX → mux_out = X → propagates everywhere
    endcase
end
// At T=0: sel=XX (not yet driven) → mux_out=X
// X propagates into downstream always_ff → q=X after first clock
// Even after reset, q may stay X if reset doesn't reach this path
 
// ✅ FIX 1: Add default case (defensive X handling)
always_comb begin
    mux_out = in_a;       // ← default: covers X input
    case (sel)
        2'b00: mux_out = in_a;
        2'b01: mux_out = in_b;
        2'b10: mux_out = in_c;
        2'b11: mux_out = in_d;
    endcase
end
 
// ✅ FIX 2: Drive sel before simulation begins
initial sel = 2'b00;   // testbench: initialize sel at T=0

// ❌ BUG: mixing blocking and non-blocking in same always_ff
always_ff @(posedge clk) begin
    tmp    = a + b;        // blocking: tmp updates immediately (Active)
    result <= tmp;        // non-blocking: RHS is current tmp (post-block?)
    status <= (tmp > 8'hFF);  // which tmp? pre- or post-blocking update?
end
 
// IEEE spec: This is non-deterministic. The value of tmp seen by <=
// depends on scheduling order within the Active region.
// VCS may give: result = new tmp (post-blocking update)
// Questa may give: result = old tmp (NBA evaluated with pre-Active values)
// Both are "correct" per IEEE — your code is ambiguous.
 
// ✅ FIX: Use only non-blocking. For intermediate calc, use automatic var.
always_ff @(posedge clk) begin
    automatic logic [8:0] tmp_local = a + b;  // local: not a net
    result <= tmp_local[7:0];               // ✅ clear and deterministic
    status <= tmp_local[8];               // ✅ overflow bit
end
 
// Or: compute in always_comb, register the result in always_ff
always_comb tmp_comb = a + b;
always_ff @(posedge clk) begin
    result <= tmp_comb[7:0];
    status <= tmp_comb[8];
end