Learnings · AMBA CHI

AMBA CHI tutorials & labs.

The most complete AMBA CHI curriculum on the internet — from cache-coherency foundations (MSI / MESI / MOESI / MESIF) through the CHI architecture (RN / HN / SN nodes, the four channels, packet-based design), every request and snoop flow, directory-based coherency, ordering, RTL design, verification, debugging, real-industry case studies, and interview mastery.

Structured curriculum

Tutorials

Learn AMBA CHI from beginner to advanced through structured tutorials.

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Hands-on practice

Labs

Practice AMBA CHI using progressively challenging hands-on labs.

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What AMBA CHI is

CHI is Arm's coherent interconnect protocol, designed for systems where many caching agents share memory. Instead of a master driving a slave over dedicated wires, CHI describes a network of nodes exchanging messages: Request Nodes issue transactions, Home Nodes act as the coherency point for a range of addresses, and Slave Nodes provide memory or peripherals behind them. Snoops, credit-based flow control and separate request, response, snoop and data channels replace the address/data handshakes of earlier AMBA buses. It is the protocol behind multi-cluster Arm SoCs where several CPUs, accelerators and caches must observe a consistent view of memory.

Why it exists

Once more than one agent caches the same memory, correctness stops being a property of any single interface. If a CPU writes a line held clean in another cache, something has to ensure the stale copy is not used. Doing that with point-to-point buses does not scale — every agent would need to see every transaction. CHI moves the problem into the interconnect: a coherency point per address region tracks who holds what, and sends snoops only where they are needed.

The part engineers get wrong

It is tempting to picture CHI as AXI plus a snoop channel, and that model breaks quickly. The difference is that coherency turns communication into distributed state management: for a given line the system must track who owns it, who holds shared copies, whether the data is dirty, and who has to be snooped before an ownership change can complete. The Home Node exists to serialise those decisions for its address range, which is why a CHI transaction is a conversation with a coherency authority rather than a transfer to a target. Debugging follows from that — an unexpected stall is usually a state or ordering question at the Home Node, not a signal-timing question on a channel.

Before you start

A solid grasp of AXI, or another channel-based bus with independent handshakes
Caches: lines, tags, hits and misses, write-back versus write-through
Helpful: exposure to a multi-core system and why stale data is a problem

What you will be able to do

Explain what Request, Home and Slave nodes each do in a transaction
Follow a snoop from issue through data transfer to ownership change
Reason about why a coherent read may be served from another cache rather than memory
Explain how credit-based flow control governs channel traffic
Approach a coherency bug by asking which node holds the line and in what state

The learning path

Why coherency needs a protocolWhat breaks when several agents cache the same line
Node typesRequest, Home and Slave nodes and their responsibilities
ChannelsRequest, response, snoop and data traffic as separate flows
SnoopsHow the interconnect asks a cache what it holds — and takes it back
Coherency and orderingWhat the protocol guarantees about visibility and order
CreditsFlow control across the network's channels
Atomics and barriersOperations that need stronger guarantees than a plain access
Verification and debugChecking coherency behaviour and diagnosing stalls

Core concepts

Request NodeThe agent that starts a transaction, and what it must track Home NodeThe coherency point that serialises decisions for an address range Slave NodeWhere memory and peripherals sit behind the coherency point Cache agentsWhich components hold cached state the protocol must track Snoop mechanismsHow the interconnect queries and reclaims cached lines Snoop channelThe dedicated traffic class snoops travel on Credit mechanismFlow control that keeps channels from overrunning receivers Atomic transactionsOperations that must complete without an intervening observer

New to AMBA CHI? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.

Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.

Follow the full curriculum

Where this leads

AMBA AXIThe non-coherent interconnect CHI builds beyond — learn its channel model first AMBA AHBWhere bus pipelining starts, several steps below CHI's network model UVMThe methodology coherency testbenches and scoreboards are built with

Standards: Arm AMBA CHI specification — The normative protocol definition; this track teaches the reasoning in original language