Learnings · AMBA APB

AMBA APB tutorials & labs.

The most complete AMBA APB curriculum — from the two-phase transfer protocol and PREADY handshake through APB2/APB3/APB4 evolution, slave RTL design, register maps, AHB/AXI bridges, performance, verification, debugging, and interview mastery.

Structured curriculum

Tutorials

Learn AMBA APB from beginner to advanced through structured tutorials.

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Hands-on practice

Labs

Practice AMBA APB using progressively challenging hands-on labs.

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What AMBA APB is

APB is the simplest member of Arm's AMBA family, and the bus most peripheral registers actually sit behind. A transfer takes two phases — SETUP, where the address and control are presented and PSEL asserts, then ACCESS, where PENABLE asserts and the transfer completes when PREADY is high. There is no pipelining, no burst, no out-of-order completion and no transaction ID. In a real SoC, high-performance traffic runs on AXI or AHB and is bridged down to APB for the timers, GPIO, UARTs and control registers where simplicity is worth more than bandwidth.

Why it exists

A peripheral register interface has very different requirements from a memory path. It is accessed rarely, it is often in a slower clock domain, and it is usually implemented by an engineer who wants to attach a block without becoming a bus expert. APB exists so that attaching a peripheral costs a handful of gates and a small state machine instead of a pipelined interface with outstanding-transaction tracking. The whole point is that it is cheap to get right.

The part engineers get wrong

PENABLE is the most misread signal on the bus. It is not a second enable or a qualifier on PSEL — it is phase information, telling the slave which of the two phases the transfer is in. PSEL alone means SETUP; PSEL with PENABLE means ACCESS. Read it that way and the protocol becomes a two-state machine. Read it as a generic enable, and you get the classic bug: a slave that acts on the address during SETUP, so a read with a side effect — a clear-on-read status bit, a FIFO pop — fires a cycle early and can fire again, destroying data the master never sees.

Before you start

Synchronous digital design and clocked state machines
The idea of an addressable register map
Helpful: any prior exposure to a bus interface, though none is assumed

What you will be able to do

Trace a complete APB read and write from a waveform, phase by phase
Explain what PSEL, PENABLE and PREADY each control, and why PENABLE is phase information
Design an APB slave with a correctly decoded register bank and a defined default
Insert wait states with PREADY without violating the protocol
Signal and propagate errors with PSLVERR
Reason about where a bridge from AHB or AXI down to APB adds latency

The learning path

Where APB fitsWhy an SoC needs a deliberately simple peripheral bus
The two-phase transferSETUP and ACCESS, and the signals that distinguish them
Address decodingTurning an address into a PSEL, and defining the unmapped case
Write and read flowsThe full sequence for each direction
PREADY and wait statesCompleting a transfer late without breaking the protocol
Error responsesPSLVERR, and what a master can do about it
BridgesHow AHB or AXI traffic reaches an APB peripheral
RTL and verificationBuilding a slave, checking it with assertions and coverage

Core concepts

The ACCESS phaseWhere the transfer actually completes, and what must be stable Address decoderPSEL generation, address mapping and the unmapped default Write flowThe full write sequence, phase by phase Read flowThe read path, and when PRDATA must be valid Why PREADY existsThe rationale for letting a slave stretch a transfer PREADY generationProducing the signal correctly inside a slave PSLVERRError signalling from the subordinate, and how it surfaces

New to AMBA APB? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.

Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.

Follow the full curriculum

Where this leads

AMBA AHBThe pipelined bus APB peripherals are usually bridged from — the next step up in complexity AMBA AXIThe high-performance interconnect that carries most SoC traffic before it reaches APB UVM RALRegister models are usually driven through an APB frontdoor in verification

Standards: Arm AMBA APB specification — The normative definition; this track teaches the reasoning behind it in original language