AMBA AHB tutorials & labs.
The most complete AMBA AHB curriculum — from the two-phase pipeline and HREADY wait states through bursts, arbitration, AHB-Lite, the AHB-to-APB bridge, and the bus matrix, into RTL design, verification, debugging, and interview mastery.
Tutorials
Learn AMBA AHB from beginner to advanced through structured tutorials.
Labs
Practice AMBA AHB using progressively challenging hands-on labs.
What AMBA AHB is
AHB sits between APB and AXI: more capable than a two-phase peripheral bus, simpler than a five-channel interconnect. Its defining feature is pipelining — the address phase of one transfer overlaps the data phase of the previous one, so the bus is doing two things at once without the full channel independence AXI introduces. It carries bursts, transfer-size and transfer-type encodings, a two-cycle error response and, in the full version, arbitration between multiple masters. AHB-Lite strips arbitration for single-master systems and is what most designs actually use.
Why it exists
A non-pipelined bus wastes a cycle presenting an address while the previous transfer's data is still moving. AHB overlaps them, which roughly doubles achievable throughput for the same clock without requiring an engineer to reason about independent channels, reordering or transaction IDs. That put it in the sweet spot for on-chip memory and moderate-bandwidth masters for a long time, and it is still where most engineers first meet pipelined bus behaviour.
The part engineers get wrong
One sentence prevents most AHB bugs: at any moment the address phase belongs to the *next* transfer while the data phase belongs to the *current* one. Engineers who reason about AHB the way they reason about APB latch the wrong address, because by the time data appears the address bus has already moved on — the slave must have captured the address and control at the end of the address phase and be using the captured copy. HREADY compounds this, because it does two jobs at once: it completes the current data phase and it advances the pipeline, so holding it low stalls both halves together rather than just delaying data.
Before you start
- Synchronous digital design and clocked state machines
- Comfort with a simple bus transfer — APB is the natural warm-up
- The idea of pipelining in hardware
What you will be able to do
- Read an AHB waveform and identify which transfer each phase belongs to
- Capture address-phase control correctly for use in the data phase
- Explain HREADY's dual role in completion and pipeline advance
- Decode HTRANS and HSIZE, and align data onto the correct byte lanes
- Work through a burst, including how it terminates early
- Generate a two-cycle error response correctly from a slave
The learning path
- Where AHB fitsBetween APB simplicity and AXI concurrency
- The address/data pipelineWhy the two phases belong to different transfers
- Control signalsHTRANS, HSIZE and what each one commits the master to
- HREADYCompletion and pipeline advance in one signal
- BurstsIncrementing and wrapping bursts, and early termination
- ResponsesOKAY and the two-cycle ERROR sequence
- ArbitrationMulti-master ownership and handover, and why AHB-Lite drops it
- RTL and verificationBuilding an AHB-Lite slave and checking it
Core concepts
New to AMBA AHB? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.
Where this leads
Standards: Arm AMBA AHB specification — The normative protocol definition behind this track