Gate Level Simulation tutorials & labs.

Gate Level Simulation, from your first netlist to a mini-SoC signoff flow. Beginner-to-advanced and debugging-heavy: understand how the gate-level netlist diverges from RTL, back-annotate real delays with SDF, and — most of all — learn to root-cause the X-propagation, reset, and timing-violation failures that only surface once gates and timing enter the picture.