Gate Level Simulation tutorials & labs.
Gate Level Simulation, from your first netlist to a mini-SoC signoff flow. Beginner-to-advanced and debugging-heavy: understand how the gate-level netlist diverges from RTL, back-annotate real delays with SDF, and — most of all — learn to root-cause the X-propagation, reset, and timing-violation failures that only surface once gates and timing enter the picture.
Tutorials
Learn Gate Level Simulation from beginner to advanced through structured tutorials.
Labs
Practice Gate Level Simulation using progressively challenging hands-on labs.
What Gate Level Simulation is
Gate-level simulation runs the synthesized netlist rather than the RTL. Instead of behavioural always blocks, the design is now instances of standard cells wired together, and with an SDF file annotated on top, each of those cells carries real propagation delays and timing checks. That makes GLS the place where questions RTL simulation cannot answer get asked: does the design still behave once synthesis has mapped it, do reset and initialization actually bring every flop to a known state, and do setup and hold checks hold under annotated delays.
Why it exists
RTL simulation assumes ideal behaviour — zero delay, and variables that start at a convenient value. Silicon does neither. Between RTL and the netlist sit synthesis transformations, clock gating, scan insertion and real cell delays, any of which can expose an assumption the RTL never tested. GLS is the last functional check before the design becomes a mask set, and it catches a specific class of problem — X propagation from uninitialised state, reset sequencing, and timing-dependent behaviour — that no amount of RTL regression will find.
The part engineers get wrong
The most valuable habit in GLS is classifying a failure before fixing it. A gate-level mismatch is not automatically a silicon bug: it may be X pessimism, where the simulator propagates unknowns more aggressively than real hardware would; it may be incomplete initialization, where the netlist has no initial values and the testbench never drove reset properly; it may be a bad SDF annotation or an unrealistic stimulus. Each of those has a different fix, and only one of them is in the RTL. Engineers who skip classification end up changing correct RTL to silence a simulation artefact.
Before you start
- RTL design and simulation experience
- An idea of what synthesis produces and what a standard cell is
- Basic static timing concepts: setup, hold and clock relationships
What you will be able to do
- Read a synthesized netlist and recognise its structure
- Annotate SDF and explain what the delays are doing to the simulation
- Classify a mismatch as X pessimism, initialization, annotation or a real bug
- Debug reset behaviour and asynchronous assertion and release at gate level
- Interpret a setup or hold violation reported during simulation
- Reason about a clock-domain-crossing structure under real delays
The learning path
- Why GLS existsThe questions RTL simulation cannot answer
- Netlist anatomyStandard cells, nets and hierarchy after synthesis
- SDF annotationAttaching real delays and timing checks
- X propagationUnknowns, pessimism and how to control them
- Reset and initializationGetting the netlist into a known state
- Timing violationsReading setup and hold failures in simulation
- CDC at gate levelAsynchronous crossings under annotated delay
- Power-aware simulationBehaviour across power domains where supported
Core concepts
New to Gate Level Simulation? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.