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SystemVerilog Fundamentals
The SystemVerilog language core — before verification.
A structured path through the SystemVerilog language itself: data types, arrays, procedural code, tasks and functions, hierarchy, packages, and interfaces. It organizes existing tutorials into one ordered sequence so you can move from Verilog to a solid SystemVerilog foundation before stepping into OOP-based verification.
8 modules53 lessons~10h 36m of reading
Prerequisites
- Comfortable with Verilog RTL and basic digital design.
What you'll be able to do
- Choose correctly between 4-state and 2-state types and reason about X/Z propagation.
- Model registers, memories, and protocol frames with arrays, queues, structs, and unions.
- Write clean procedural RTL and testbench logic using tasks, functions, and process control.
- Structure designs with modules, packages, and interfaces with modports.
Competencies you'll develop
SystemVerilog language foundations
Set up a SystemVerilog toolchain and write, compile, and run a first program with correct module and testbench anatomy.
4-state & 2-state data modeling
Choose correctly between 4-state and 2-state types and reason about X/Z propagation, width, and signedness.
Arrays & aggregate data structures
Model registers, memories, and protocol frames with packed/unpacked arrays, dynamic arrays, queues, structs, and unions.
Operators & expressions
Apply SystemVerilog operators and expression semantics, including X/Z-aware equality and signed vs. unsigned evaluation.
Procedural control flow
Write correct procedural RTL and testbench logic with the always variants, blocking/nonblocking assignment, and control statements.
Tasks & functions
Structure reusable behavior with tasks and functions, understanding automatic vs. static lifetime and argument passing.
Modules & hierarchy
Compose designs from modules and packages with correct instantiation, parameterization, and scope.
Interfaces & modports
Bundle related signals with interfaces and enforce direction and access with modports.
Curriculum
01
Foundations
4 lessons- 01What is SystemVerilog?What SystemVerilog is, why it was created, its history, and its critical role in modern chip design and verification.
- 02SystemVerilog vs VerilogDeep technical comparison — data types, always blocks, interfaces, OOP, assertions, packages.
- 03Tool SetupQuestaSim, VCS, Xcelium, Verilator, EDA Playground, VS Code, GTKWave — install and first run.
- 04Your First SystemVerilog ProgramBuild your first SV program from scratch — module anatomy, ports, initial blocks, testbench structure.
02
Data Types
9 lessons- 054-State vs 2-State Typeslogic, bit, reg, wire — X/Z propagation, simulation behavior, synthesis implications.
- 06Integer Typesbyte, shortint, int, longint, integer, time — signed behavior, overflow, 2-state vs 4-state.
- 07Real & Shortreal TypesIEEE 754, precision, epsilon comparison, $realtobits, timing calculations.
- 08String Type & Methodslen, substr, toupper, compare, atoi, itoa, $sformatf — message generation patterns.
- 09User-Defined Types with typedefNamed aliases, parameterized types, forward declarations, package-level typedefs.
- 10Enumeration TypesFSM state encoding, enum methods, $cast, waveform naming, unique case.
- 11Structures — Packed & UnpackedRegister field modeling, protocol frame packing, struct literals.
- 12Unions & Tagged UnionsPacked unions, overlapping bit fields, tagged union type safety, protocol packet decoding.
- 13Type Casting & ConversionStatic cast, $signed, $unsigned, $cast, implicit conversions, width truncation.
03
Arrays
5 lessons- 14Fixed-Size ArraysPacked vs unpacked, multi-dimensional, initialization, foreach, system functions.
- 15Dynamic ArraysRuntime sizing with new[], delete(), resize, copy semantics, constraints.
- 16Associative ArraysArbitrary key types, exists(), delete(), iteration, sparse memory, scoreboard lookup.
- 17Queuespush/pop, bounded queues, slicing, insert/delete, FIFO modeling.
- 18Array Methodssort, rsort, find, find_index, sum, min, max, unique — with-clause expressions.
04
Operators & Expressions
10 lessons- 19Arithmetic OperatorsPre/post increment & decrement, X-propagation, signed vs unsigned.
- 20Relational & Equality Operators== vs === with X/Z values, the scoreboard false-pass bug, signed vs unsigned.
- 21Logical Operators&&, ||, ! — short-circuit evaluation, X propagation, common confusion with bitwise.
- 22Bitwise Operators&, |, ^, ~, ~^ — masking, bit manipulation, XOR parity, X propagation.
- 23Reduction Operators&, |, ^, ~&, ~|, ~^ — parity generation, one-hot checking, X propagation.
- 24Shift Operators<<, >>, <<<, >>> — logical vs arithmetic right shift, signed behavior, sign extension.
- 25Concatenation, Replication & Conditional{}, {N{}}, ?: — bus assembly, field packing, X-merge behavior.
- 26Inside OperatorSet membership testing, ranges, arrays, X/Z wildcard behavior, constraint usage.
- 27Wildcard Equality — ==? and !=?X/Z don't-care matching, mask-based pattern matching, comparison with casex/casez.
- 28Operator PrecedenceComplete precedence table, associativity rules, classic precedence traps.
05
Procedural Statements
6 lessons- 29Procedural Blocksinitial, always, always_comb, always_ff, always_latch — what hardware each one infers.
- 30if-else & Unique/Priority ModifiersHardware inferred, simulation checks, coverage and synthesis safety.
- 31case, casex, casez, unique, priorityHardware inference, don't-care matching, modifier safety.
- 32Loopsfor, while, do-while, repeat, forever, foreach — synthesisable vs simulation-only.
- 33break, continue, return, disableLoop control — synthesis vs simulation behavior.
- 34Blocking vs Non-Blocking Assignments= vs <=, the NBA scheduler, the golden rule, race conditions.
06
Tasks & Functions
7 lessons- 35Tasks vs. Functions — When to Use WhichThe core distinction — timing controls, return values, calling syntax, and exactly when to pick each one.
- 36Function Declarations & Return ValuesReturn types, return statement vs named variable, early return, arguments, RTL usage, recursion, packages, synthesis deep dive, 7 debugging labs, and interview Q&A.
- 37Task Declarations & Time-Consuming CallsTask anatomy, timing controls (#, @, wait), arguments, disable, fork-join, class tasks, and APB driver patterns.
- 38Automatic vs. Static LifetimeWhat `lifetime` means, default rules, recursion's need for `automatic`, the static-task concurrent-call bug, and decision rules.
- 39Pass by Value vs. Pass by ReferenceCopy vs alias semantics, `ref` and `const ref`, inout-vs-ref timing, large-array performance, and when each is required.
- 40Default Argument ValuesDefault values for function/task arguments, the ordering rule, named-argument calls, defaults from parameters, and API design patterns.
- 41void Functions & System Tasks OverviewFunctions with no return value, the full system task catalogue ($display, $strobe, $monitor, $finish, randomization, file I/O), and timing semantics.
07
Modules & Hierarchy
7 lessons- 42Module Definition & InstantiationModule anatomy, port lists, hierarchical design, multi-instance wiring, named/positional/wildcard connections, and instance arrays.
- 43Port Types — input, output, inout, refDirection rules, port data types, tri-state inout, output vs output reg, ref for large structs, and synthesis vs simulation semantics.
- 44Named & Positional Port ConnectionsThree connection styles — positional, named, and .* — with width/type mismatch handling, inout patterns, 6 debugging labs, and refactoring guidance.
- 45Parameters & Localparamsparameter vs localparam, $clog2 derivation, typed parameters, naming conventions, hierarchical sizing, and 5 debugging labs across the parameter contract.
- 46Parameter Overrides — defparam & # NotationNamed vs positional overrides, why defparam is deprecated, type-checked parameters, string-parameter pitfalls, and hierarchy propagation.
- 47Generate Constructs — for, if, caseStructural unrolling at elaboration, genvar, named generate blocks, feature switches via generate-if, multi-way generate-case, and 5 debugging labs.
- 48Hierarchical References & $rootSymbolic pointers vs wire connections, $root scope, force/release semantics, testbench backdoor patterns, why upward references break encapsulation, and 5 debugging labs.
08
Interfaces
5 lessons- 49Introduction to InterfacesWhy interfaces exist, signal bundling, the elimination of long port lists, and the backbone abstraction of every modern UVM testbench.
- 50Modport — Restricting Port DirectionsPer-role direction control on interface signals, master/slave/monitor modports, task imports, and structural enforcement of bus role contracts.
- 51Clocking BlocksEliminating TB-DUT races at the clock edge: input/output skews, the ##N operator, default clocking, and the canonical Preponed-sample/Re-NBA-drive pattern.
- 52Virtual InterfacesThe bridge between module-world interfaces and class-world UVM components; config_db handoff, modport-qualified handles, and 5 debugging labs.
- 53Interface Arrays & Parameterised InterfacesScaling testbenches to N channels with interface arrays, parameterised widths, multi-channel UVM patterns, and per-channel coverage.
Completion: work through all 8 required modules (53 lessons) to develop the 8 competencies above. Reading is the medium — there is nothing to enrol in or unlock.
Assessment
PlannedHow understanding in this program would be checked. Assessment measures engineering reasoning against the competencies above — it is not part of the reading, and there is nothing to start or score here.
SystemVerilog Fundamentals — mastery assessment
Reasoning challengeA reasoning-first assessment across the SystemVerilog language core: data modeling, aggregate structures, procedural code, tasks and functions, hierarchy, and interfaces.
Per-module knowledge checks
- Foundations
- Data Types
- Arrays
- Operators & Expressions
- Procedural Statements
- Tasks & Functions
- Modules & Hierarchy
- Interfaces